linux-kernel - Re: [PATCH 2/4] soc: Mediatek: Add SCPSYS power domain driver

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Message-ID: <1426043791.24243.9.camel@mtksdaap41>
Date:	Wed, 11 Mar 2015 11:16:31 +0800
From:	James Liao <jamesjj.liao@...iatek.com>
To:	Sascha Hauer <s.hauer@...gutronix.de>
CC:	Kevin Hilman <khilman@...nel.org>,
	<linux-arm-kernel@...ts.infradead.org>,
	<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
	Matthias Brugger <matthias.bgg@...il.com>,
	<linux-mediatek@...ts.infradead.org>, <kernel@...gutronix.de>
Subject: Re: [PATCH 2/4] soc: Mediatek: Add SCPSYS power domain driver

Hi,

On Tue, 2015-03-10 at 10:41 +0100, Sascha Hauer wrote:
> On Mon, Mar 09, 2015 at 02:35:03PM -0700, Kevin Hilman wrote:
> > Sascha Hauer <s.hauer@...gutronix.de> writes:
> > 
> > > Signed-off-by: Sascha Hauer <s.hauer@...gutronix.de>
> > 
> > A bit of a changelog here would be useful describing this driver, that
> > it's only covering part of the device (e.g. power controller) with more
> > to come, dependency on the syscon driver, etc.
> > 
> > > +/*
> > > + * The Infracfg unit has bus protection bits. We enable the bus protection
> > > + * for disabled power domains so that the system does not hang when some unit
> > > + * accesses the bus while in power down.
> > > + */
> > 
> > Hmm, why don't you want to know if some device is accessing another
> > device which is in a domain that is powered down?   Seems like this is a
> > good way to hide real bugs.
> 
> How I understand it the system just hangs on erroneous accesses without
> these protection bits enabled, so enabling them at least makes sure we
> can output something.
> I must admit though that my understanding of these bits is quite limited
> and the only user of this driver I have available here (audio) doesn't
> make use of these protection bits, so I can't test here.
> 
> James, could you shed some light on this issue?

I asked our designer about the bus protection feature, here is his
response:

"
It's for unexpected signal glitch in Power switch process.

During Power switch process, we have clock switch, reset, isolation
enable/disable and  power switch involved where the transition of
asynchronous reset and  isolation is the most critical one,  which have
risk to introduce a unexpected short period signal transition from
MTCMOS’s interface to other alive HW . 
"

That means it protects unexpected bus accessing from HW, not from SW. So
it will not hide bugs from wrong SW access.


Best regards,

James

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