Message-Id: <1426202167-30598-1-git-send-email-vikas.shivappa@linux.intel.com>
Date:	Thu, 12 Mar 2015 16:16:00 -0700
From:	Vikas Shivappa <vikas.shivappa@...ux.intel.com>
To:	vikas.shivappa@...el.com
Cc:	x86@...nel.org, linux-kernel@...r.kernel.org, hpa@...or.com,
	tglx@...utronix.de, mingo@...nel.org, tj@...nel.org,
	peterz@...radead.org, matt.fleming@...el.com, will.auld@...el.com,
	glenn.p.williamson@...el.com, kanaka.d.juvva@...el.com,
	vikas.shivappa@...ux.intel.com
Subject: [PATCH V5 0/7] x86/intel_rdt: Intel Cache Allocation Technology

This patch adds a new cgroup subsystem to support the new Cache Allocation 
Technology (CAT) feature found in future Intel Xeon Intel processors. CAT is 
part of Resource Director Technology(RDT) or
Platform Shared resource control which provides support to control
Platform shared resources like cache.
More information can be found in the *Intel SDM Volume 3 section 17.15*.

This patch series is *dependent* on the V5 patches for Intel Cache QOS
Monitoring from Matt since the series also implements a common
software cache for the IA32_PQR_MSR :
https://lkml.kernel.org/r/1422038748-21397-1-git-send-email-matt@codeblueprint.co.uk

*All the patches will apply on 4.0-rc3*.

I have added a bit of code that was left out in this series. The h/w 
provides per package CLOSIDs but OS just treats them as global to
simplify the handling.  When the corresponding cache bitmasks are 
changed the change needs to be propagated to all the packages.  CLOSID 
update to IA32_PQR_MSR is already done on a per-cpu basis.

Changes in v5:
- Added support to propagate the cache bit mask update for each
  package.
- Removed the cache bit mask reference in the intel_rdt structure as
  we already maintain a separate closid<->cbm mapping.
- Made a few coding convention changes and added an
  assertion for cgroup count while freeing the CLOSID.

Changes in V4:
- Integrated with the latest V5 CMT patches.
- Changed naming of cgroup to rdt(resource director technology) from
  cat(cache allocation technology). This was done as the RDT is the
  umbrella term for platform shared resources allocation. Hence in
  future it would be easier to add resource allocation to the same 
  cgroup
- Naming changes also applied to a lot of other data structures/APIs.
- Added documentation on cgroup usage for cache allocation to address
  a lot of questions from various academic and industry regarding 
  cache allocation usage.

Changes in V3:
- Implements a common software cache for IA32_PQR_MSR
- Implements support for hsw CAT enumeration. This does not use the brand 
strings like earlier version but does a probe test. The probe test is done only 
on hsw family of processors
- Made a few coding convention, name changes
- Check for lock being held when ClosID manipulation happens

Changes in V2:
- Removed HSW specific enumeration changes. Plan to include it later as a
  separate patch.  
- Fixed the code in prep_arch_switch to be specific for x86 and removed
  x86 defines.
- Fixed cbm_write to not write all 1s when a cgroup is freed.
- Fixed one possible memory leak in init.  
- Changed some of manual bitmap
  manipulation to use the predefined bitmap APIs to make code more readable
- Changed name in sources from cqe to cat
- Global cat enable flag changed to static_key and disabled cgroup early_init
      
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