linux-kernel - Re: [RFC] powerpc: e6500 optimised copy_to_user/copy_from

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Message-ID: <1426202791.2772.1.camel@ellerman.id.au>
Date:	Fri, 13 Mar 2015 10:26:31 +1100
From:	Michael Ellerman <mpe@...erman.id.au>
To:	Kim Phillips <kim.phillips@...escale.com>
Cc:	Benjamin Herrenschmidt <benh@...nel.crashing.org>,
	Paul Mackerras <paulus@...ba.org>, scottwood@...escale.com,
	Anton Blanchard <anton@...ba.org>,
	linuxppc-dev@...ts.ozlabs.org, linux-kernel@...r.kernel.org
Subject: Re: [RFC] powerpc: e6500 optimised copy_to_user/copy_from_user

On Thu, 2015-03-12 at 17:45 -0500, Kim Phillips wrote:
> This mimics commit a66086b8197da8dc83b698642d5947ff850e708d "powerpc:
> POWER7 optimised copy_to_user/copy_from_user using VMX", but for
> the e6500, or BOOK3S_64.  Changes have been made for the smaller
> cacheline size (64 bytes on e6500), and data cache block touch (dcbt)
> instructions have been rewritten to prefetch 8 lines ahead, based
> on preliminary benchmark results and perf -e L1-dcache-prefetches
> and misses observations.
> 
> We see a gain of 5% in large netperf benchmarks between two T4240s,
> both in terms of throughput, and latency.  The same netperf
> lo(opback) test improves 27%.
> 
> Anton's microbenchmark results show a clear linear improvement path
> with sizes 32KB and above, where, below that, the additional overhead
> over the existing copyuser_64 implementation shows its head: e.g., 6%
> for 1448 byte copies.  The observed transfer sizes under large,
> netperf benchmarks show the TCP stack is invoking copies on the
> order of a few 10's of KB, however. 1MB transfers are 30% better-off
> on wall clock time.
> 
> RFC because of the following known issues:
> - unsure if PPC_BOOK3E_64 vs. PPC_BOOK3S_64 build-time switch to
>   re-target __copy_tofrom_user_vmx is appropriate (ppc64_defconfig
>   builds fine, however)

That's fine, a combined kernel is not really on the horizon.

> - syscalls report deficits when folding vmx_unaligned_copy to a 64B
>   cacheline (undone for this RFC)
> - any consideration for the e5500?
> - asm branch label re-enumeration
> - ..I'm sure I've missed another couple of things, possibly
> including how to fix lower-sized transfer performance

Well the big issue for me is the code duplication. The diff between the
original and yours is not small, but it looks like doing a combined version
*should* be possible?

If you take out the 8 line prefetch changes it looks like it's just the
cacheline size that is the issue?

cheers



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