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Message-ID: <55031585.2030908@amd.com>
Date: Fri, 13 Mar 2015 11:51:17 -0500
From: Joel Schopp <joel.schopp@....com>
To: <jesse.larrew@....com>, <x86@...nel.org>
CC: Tony Luck <tony.luck@...el.com>, Borislav Petkov <bp@...en8.de>,
"Thomas Gleixner" <tglx@...utronix.de>,
Ingo Molnar <mingo@...hat.com>,
"H. Peter Anvin" <hpa@...or.com>, <linux-edac@...r.kernel.org>,
<linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v2] mce: use safe MSR accesses
On 03/13/2015 11:03 AM, jesse.larrew@....com wrote:
> From: Jesse Larrew <jesse.larrew@....com>
>
> Certain MSRs are only relevant to a kernel in host mode, and kvm had
> chosen not to implement these MSRs at all for guests. If a guest kernel
> ever tried to access these MSRs, the result was a general protection
> fault.
>
> KVM will be separately patched to return 0 when these MSRs are read,
> and this patch ensures that MSR accesses are tolerant of exceptions.
>
> Signed-off-by: Jesse Larrew <jesse.larrew@....com>
> ---
> arch/x86/kernel/cpu/mcheck/mce.c | 11 +++--------
> 1 file changed, 3 insertions(+), 8 deletions(-)
>
> diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
> index 61a9668ce..2737ced 100644
> --- a/arch/x86/kernel/cpu/mcheck/mce.c
> +++ b/arch/x86/kernel/cpu/mcheck/mce.c
> @@ -1540,7 +1540,7 @@ static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
> if (c->x86 == 0x15 &&
> (c->x86_model >= 0x10 && c->x86_model <= 0x1f)) {
> int i;
> - u64 val, hwcr;
> + u64 hwcr;
> bool need_toggle;
> u32 msrs[] = {
> 0x00000413, /* MC4_MISC0 */
> @@ -1556,13 +1556,8 @@ static int __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
> wrmsrl(MSR_K7_HWCR, hwcr | BIT(18));
>
> for (i = 0; i < ARRAY_SIZE(msrs); i++) {
> - rdmsrl(msrs[i], val);
> -
> - /* CntP bit set? */
> - if (val & BIT_64(62)) {
> - val &= ~BIT_64(62);
> - wrmsrl(msrs[i], val);
> - }
> + /* Clear CntP bit safely */
> + msr_clear_bit(msrs[i], 62);
> }
>
> /* restore old settings */
I like it.
Reviewed-by: Joel Schopp <joel.schopp@....com>
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