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Date: Mon, 16 Mar 2015 15:20:32 +0100 From: Gabriel FERNANDEZ <gabriel.fernandez@...com> To: Rob Herring <robh+dt@...nel.org>, Pawel Moll <pawel.moll@....com>, Mark Rutland <mark.rutland@....com>, Ian Campbell <ijc+devicetree@...lion.org.uk>, Kumar Gala <galak@...eaurora.org>, Srinivas Kandagatla <srinivas.kandagatla@...il.com>, Maxime Coquelin <maxime.coquelin@...com>, Patrice Chotard <patrice.chotard@...com>, Russell King <linux@....linux.org.uk>, Bjorn Helgaas <bhelgaas@...gle.com>, Mohit Kumar <mohit.kumar@...com>, Jingoo Han <jg1.han@...sung.com>, Lucas Stach <l.stach@...gutronix.de>, Fabrice Gasnier <fabrice.gasnier@...com>, Kishon Vijay Abraham I <kishon@...com>, Andrew Morton <akpm@...ux-foundation.org>, " David S. Miller" <davem@...emloft.net>, Greg KH <gregkh@...uxfoundation.org>, Mauro Carvalho Chehab <mchehab@....samsung.com>, Joe Perches <joe@...ches.com>, Tejun Heo <tj@...nel.org>, Arnd Bergmann <arnd@...db.de>, Viresh Kumar <viresh.kumar@...aro.org>, Thierry Reding <treding@...dia.com>, Phil Edworthy <phil.edworthy@...esas.com>, Minghuan Lian <Minghuan.Lian@...escale.com>, Tanmay Inamdar <tinamdar@....com>, <m-karicheri2@...com>, Sachin Kamat <sachin.kamat@...sung.com>, Andrew Lunn <andrew@...n.ch>, Liviu Dudau <liviu.dudau@....com> Cc: devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org, kernel@...inux.com, linux-pci@...r.kernel.org, Lee Jones <lee.jones@...aro.org>, Gabriel Fernandez <gabriel.fernandez@...aro.org> Subject: [PATCH v2 2/5] PCI: st: Add Device Tree bindings for sti pcie sti pcie is built around a Synopsis Designware PCIe IP. Signed-off-by: Fabrice Gasnier <fabrice.gasnier@...com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@...aro.org> --- Documentation/devicetree/bindings/pci/st-pcie.txt | 54 +++++++++++++++++++++++ 1 file changed, 54 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/st-pcie.txt diff --git a/Documentation/devicetree/bindings/pci/st-pcie.txt b/Documentation/devicetree/bindings/pci/st-pcie.txt new file mode 100644 index 0000000..94aae2d --- /dev/null +++ b/Documentation/devicetree/bindings/pci/st-pcie.txt @@ -0,0 +1,54 @@ +STMicroelectronics STi PCIe controller + +This PCIe host controller is based on the Synopsis Designware PCIe IP +and thus inherits all the common properties defined in designware-pcie.txt. + +Required properties: + - compatible: "st,stih407-pcie" + - reg: base address and length of the pcie controller, mem-window address + and length available to the controller. + - interrupts: A list of interrupt outputs of the controller. Must contain an + entry for each entry in the interrupt-names property. + - interrupt-names: Should be "msi". STi interrupt that is asserted when an + MSI is received. + - st,syscfg : should be a phandle of the syscfg node. Also contains syscfg + offset for IP configuration. + - resets, reset-names: the power-down and soft-reset lines of PCIe IP. + Associated names must be "powerdown" and "softreset". + - phys, phy-names: the phandle for the PHY device. + Associated name must be "pcie" + +Optional properties: + - reset-gpio: a GPIO spec to define which pin is connected to the bus reset. + +Example: + +pcie0: pcie@...0000 { + compatible = "st,stih407-pcie", "snps,dw-pcie"; + device_type = "pci"; + reg = <0x09b00000 0x4000>, /* dbi cntrl registers */ + <0x2fff0000 0x00010000>, /* configuration space */ + <0x40000000 0x80000000>; /* lmi mem window */ + reg-names = "dbi", "config", "mem-window"; + st,syscfg = <&syscfg_core 0xd8 0xe0>; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x00000800 0 0x2fff0000 0x2fff0000 0 0x00010000 /* configuration space */ + 0x82000000 0 0x20000000 0x20000000 0 0x0FFF0000>; /* non-prefetchable memory */ + num-lanes = <1>; + interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &intc GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, /* INT A */ + <0 0 0 2 &intc GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, /* INT B */ + <0 0 0 3 &intc GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, /* INT C */ + <0 0 0 4 &intc GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; /* INT D */ + + resets = <&powerdown STIH407_PCIE0_POWERDOWN>, + <&softreset STIH407_PCIE0_SOFTRESET>; + reset-names = "powerdown", + "softreset"; + phys = <&phy_port0 PHY_TYPE_PCIE>; + phy-names = "pcie"; +}; -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@...r.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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