linux-kernel - [PATCH][RESEND] drivers/base: cacheinfo: validate device node for all the caches

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Message-Id: <1426613326-7201-1-git-send-email-sudeep.holla@arm.com>
Date:	Tue, 17 Mar 2015 17:28:46 +0000
From:	Sudeep Holla <sudeep.holla@....com>
To:	Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
	linux-kernel@...r.kernel.org
Cc:	Sudeep Holla <sudeep.holla@....com>
Subject: [PATCH][RESEND] drivers/base: cacheinfo: validate device node for all the caches

On architectures that depend on DT for obtaining cache hierarcy, we need
to validate the device node for all the cache indices, failing to do so
might result in wrong information being exposed to the userspace.

This is quite possible on initial/incomplete versions of the device
trees. In such cases, it's better to bail out if all the required device
nodes are not present.

This patch adds checks for the validation of device node for all the
caches and doesn't initialise the cacheinfo if there's any error.

Cc: Greg Kroah-Hartman <gregkh@...uxfoundation.org>
Reported-by: Mark Rutland <mark.rutland@....com>
Acked-by: Mark Rutland <mark.rutland@....com>
Signed-off-by: Sudeep Holla <sudeep.holla@....com>
---
 drivers/base/cacheinfo.c | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

Hi Greg,

Can you please pick this up as a bug fix ?

Without this there's possibility that erroneous information is exposed
to userspace on architecture depending on DT especially if DT lacks
cache hierarchy information.

There are many arm64 device trees without cache hierarchy which results
in exposing wrong cacheinfo to the user space. It would be good to get
this included as bug fix for 4.0

This was previously posted a while ago[1]

Regards,
Sudeep

[1] https://lkml.org/lkml/2015/2/16/264
diff --git a/drivers/base/cacheinfo.c b/drivers/base/cacheinfo.c
index 6e64563361f0..9c2ba1c97c42 100644
--- a/drivers/base/cacheinfo.c
+++ b/drivers/base/cacheinfo.c
@@ -62,15 +62,21 @@ static int cache_setup_of_node(unsigned int cpu)
 		return -ENOENT;
 	}

-	while (np && index < cache_leaves(cpu)) {
+	while (index < cache_leaves(cpu)) {
 		this_leaf = this_cpu_ci->info_list + index;
 		if (this_leaf->level != 1)
 			np = of_find_next_cache_node(np);
 		else
 			np = of_node_get(np);/* cpu node itself */
+		if (!np)
+			break;
 		this_leaf->of_node = np;
 		index++;
 	}
+
+	if (index != cache_leaves(cpu)) /* not all OF nodes populated */
+		return -ENOENT;
+
 	return 0;
 }

@@ -189,8 +195,11 @@ static int detect_cache_attributes(unsigned int cpu)
 	 * will be set up here only if they are not populated already
 	 */
 	ret = cache_shared_cpu_map_setup(cpu);
-	if (ret)
+	if (ret) {
+		pr_warn("Unable to detect cache hierarcy from DT for CPU %d\n",
+			cpu);
 		goto free_ci;
+	}
 	return 0;

 free_ci:
-- 
1.9.1

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