linux-kernel - Re: [PATCH 2/2] pinctrl: Add Pistachio SoC pin control driver

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Message-ID: <CACRpkdbXm_aPQU0-wV8yASts7n4QBd1dAe8-d40g2xy2KBAKEQ@mail.gmail.com>
Date:	Thu, 19 Mar 2015 09:42:16 +0100
From:	Linus Walleij <linus.walleij@...aro.org>
To:	Andrew Bresticker <abrestic@...omium.org>
Cc:	Alexandre Courbot <gnurou@...il.com>,
	Ralf Baechle <ralf@...ux-mips.org>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	"linux-gpio@...r.kernel.org" <linux-gpio@...r.kernel.org>,
	Linux MIPS <linux-mips@...ux-mips.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	Ezequiel Garcia <ezequiel.garcia@...tec.com>,
	James Hartley <james.hartley@...tec.com>,
	James Hogan <james.hogan@...tec.com>,
	Damien Horsley <Damien.Horsley@...tec.com>,
	Govindraj Raja <govindraj.raja@...tec.com>
Subject: Re: [PATCH 2/2] pinctrl: Add Pistachio SoC pin control driver

On Tue, Mar 17, 2015 at 5:56 PM, Andrew Bresticker
<abrestic@...omium.org> wrote:
[Me]
>> Sorry if I don't really know how things work now... :(
>> It seems like a logical way to me.
(...)
> 4) The ->set_mux() op must set the proper function for the pin.
> 5) The ->set_mux() op must also disable the GPIO function for the pin.
> To disable the GPIO function, the pinctrl driver must map the pin to a
> GPIO bank/offset and disable the GPIO via the GPIO bank's GPIO_EN
> register.

That sounds like the"GPIO" registers are actually involved in any
muxing usecase, meaning there is not really a clean split between
the pinctrl and GPIO hardware, the case I refer to as "GPIO mode
pitfalls" in Documentation/pinctrl.txt.

In such cases both halves of the driver(s) need to be aware of
the other, and that is what you seem to be wanting to achieve.

So I was wrong in thinking the GPIO device could be a separate
subdevice, the two parts are too dependent on each other.
So keep a single probe() function and let the two driver halves
poke into each others' registers.

Sorry for the fuzz...

Yours,
Linus Walleij
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