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Message-Id: <1426771061-28103-1-git-send-email-sudipm.mukherjee@gmail.com>
Date: Thu, 19 Mar 2015 18:47:40 +0530
From: Sudip Mukherjee <sudipm.mukherjee@...il.com>
To: Greg Kroah-Hartman <gregkh@...uxfoundation.org>
Cc: linux-fbdev@...r.kernel, devel@...verdev.osuosl.org,
linux-kernel@...r.kernel.org,
Sudip Mukherjee <sudipm.mukherjee@...il.com>
Subject: [PATCH 1/2] staging: sm750fb: remove 750LE code
750LE is a special version of the hardware with Ip Core and
Silicon Motion is making this hardware only for Huawei. It is not
available to anyone else.
So its better to remove the codes related to SM750LE.
Signed-off-by: Sudip Mukherjee <sudip@...torindia.org>
---
this patch will generate warning from checkpatch. but since those were
already there in the file so nothing has been done about it.
and I am not sure if this patch will apply or not as some patches
of Lorenzo Stoakes and Ragavendra Nagraj are already pending.
if those patches are already applied then this will not apply.
drivers/staging/sm750fb/ddk750_chip.c | 64 ++++++----------------------------
drivers/staging/sm750fb/ddk750_mode.c | 19 +++-------
drivers/staging/sm750fb/ddk750_swi2c.c | 3 --
drivers/staging/sm750fb/sm750.c | 9 ++---
drivers/staging/sm750fb/sm750_hw.c | 55 ++++-------------------------
5 files changed, 24 insertions(+), 126 deletions(-)
diff --git a/drivers/staging/sm750fb/ddk750_chip.c b/drivers/staging/sm750fb/ddk750_chip.c
index 33add64..a8ebedd 100644
--- a/drivers/staging/sm750fb/ddk750_chip.c
+++ b/drivers/staging/sm750fb/ddk750_chip.c
@@ -20,22 +20,14 @@ logical_chip_type_t getChipType(void)
physicalID = devId750;//either 0x718 or 0x750
physicalRev = revId750;
- if (physicalID == 0x718)
- {
- chip = SM718;
- }
- else if (physicalID == 0x750)
- {
- chip = SM750;
- /* SM750 and SM750LE are different in their revision ID only. */
- if (physicalRev == SM750LE_REVISION_ID){
- chip = SM750LE;
- }
- }
- else
- {
- chip = SM_UNKNOWN;
- }
+ if (physicalID == 0x750)
+ {
+ chip = SM750;
+ }
+ else
+ {
+ chip = SM_UNKNOWN;
+ }
return chip;
}
@@ -94,10 +86,6 @@ unsigned int getPllValue(clock_type_t clockType, pll_value_t *pPLL)
unsigned int getChipClock(void)
{
pll_value_t pll;
-#if 1
- if(getChipType() == SM750LE)
- return MHz(130);
-#endif
return getPllValue(MXCLK_PLL, &pll);
}
@@ -112,11 +100,6 @@ void setChipClock(unsigned int frequency)
{
pll_value_t pll;
unsigned int ulActualMxClk;
-#if 1
- /* Cheok_0509: For SM750LE, the chip clock is fixed. Nothing to set. */
- if (getChipType() == SM750LE)
- return;
-#endif
if (frequency != 0)
{
@@ -143,11 +126,7 @@ void setChipClock(unsigned int frequency)
void setMemoryClock(unsigned int frequency)
{
unsigned int ulReg, divisor;
- #if 1
- /* Cheok_0509: For SM750LE, the memory clock is fixed. Nothing to set. */
- if (getChipType() == SM750LE)
- return;
-#endif
+
if (frequency != 0)
{
/* Set the frequency to the maximum frequency that the DDR Memory can take
@@ -193,11 +172,7 @@ void setMemoryClock(unsigned int frequency)
void setMasterClock(unsigned int frequency)
{
unsigned int ulReg, divisor;
- #if 1
- /* Cheok_0509: For SM750LE, the memory clock is fixed. Nothing to set. */
- if (getChipType() == SM750LE)
- return;
-#endif
+
if (frequency != 0)
{
/* Set the frequency to the maximum frequency that the SM750 engine can
@@ -237,10 +212,6 @@ unsigned int ddk750_getVMSize(void)
unsigned int reg;
unsigned int data;
- /* sm750le only use 64 mb memory*/
- if(getChipType() == SM750LE)
- return MB(64);
-
/* for 750,always use power mode0*/
reg = PEEK32(MODE0_GATE);
reg = FIELD_SET(reg,MODE0_GATE,GPIO,ON);
@@ -291,12 +262,6 @@ int ddk750_initHw(initchip_param_t * pInitParam)
ulReg = FIELD_SET(ulReg,VGA_CONFIGURATION,PLL,PANEL);
ulReg = FIELD_SET(ulReg,VGA_CONFIGURATION,MODE,GRAPHIC);
POKE32(VGA_CONFIGURATION,ulReg);
- }else{
-#if defined(__i386__) || defined( __x86_64__)
- /* set graphic mode via IO method */
- outb_p(0x88,0x3d4);
- outb_p(0x06,0x3d5);
-#endif
}
/* Set the Main Chip Clock */
@@ -444,15 +409,6 @@ unsigned int calcPllValue(unsigned int request_orig,pll_value_t *pll)
unsigned int tmpClock,ret;
pllcalparam * xparm;
-#if 1
- if (getChipType() == SM750LE)
- {
- /* SM750LE don't have prgrammable PLL and M/N values to work on.
- Just return the requested clock. */
- return request_orig;
- }
-#endif
-
ret = 0;
miniDiff = ~0;
request = request_orig / 1000;
diff --git a/drivers/staging/sm750fb/ddk750_mode.c b/drivers/staging/sm750fb/ddk750_mode.c
index 2e418fb..44e346a 100644
--- a/drivers/staging/sm750fb/ddk750_mode.c
+++ b/drivers/staging/sm750fb/ddk750_mode.c
@@ -107,17 +107,13 @@ static int programModeRegisters(mode_parameter_t * pModeParam,pll_value_t * pll)
FIELD_SET(0,CRT_DISPLAY_CTRL,PLANE,ENABLE);
- if(getChipType() == SM750LE){
- displayControlAdjust_SM750LE(pModeParam,ulTmpValue);
- }else{
- ulReg = PEEK32(CRT_DISPLAY_CTRL)
- & FIELD_CLEAR(CRT_DISPLAY_CTRL,VSYNC_PHASE)
- & FIELD_CLEAR(CRT_DISPLAY_CTRL,HSYNC_PHASE)
- & FIELD_CLEAR(CRT_DISPLAY_CTRL,TIMING)
- & FIELD_CLEAR(CRT_DISPLAY_CTRL,PLANE);
+ ulReg = PEEK32(CRT_DISPLAY_CTRL)
+ & FIELD_CLEAR(CRT_DISPLAY_CTRL, VSYNC_PHASE)
+ & FIELD_CLEAR(CRT_DISPLAY_CTRL, HSYNC_PHASE)
+ & FIELD_CLEAR(CRT_DISPLAY_CTRL, TIMING)
+ & FIELD_CLEAR(CRT_DISPLAY_CTRL, PLANE);
POKE32(CRT_DISPLAY_CTRL,ulTmpValue|ulReg);
- }
}
else if(pll->clockType == PRIMARY_PLL)
@@ -193,11 +189,6 @@ int ddk750_setModeTiming(mode_parameter_t * parm,clock_type_t clock)
pll.clockType = clock;
uiActualPixelClk = calcPllValue(parm->pixel_clock,&pll);
- if(getChipType() == SM750LE){
- /* set graphic mode via IO method */
- outb_p(0x88,0x3d4);
- outb_p(0x06,0x3d5);
- }
programModeRegisters(parm,&pll);
return 0;
}
diff --git a/drivers/staging/sm750fb/ddk750_swi2c.c b/drivers/staging/sm750fb/ddk750_swi2c.c
index 8557cce..b162ced 100644
--- a/drivers/staging/sm750fb/ddk750_swi2c.c
+++ b/drivers/staging/sm750fb/ddk750_swi2c.c
@@ -410,9 +410,6 @@ long swI2CInit(
if ((i2cClkGPIO > 31) || (i2cDataGPIO > 31))
return -1;
- if (getChipType() == SM750LE)
- return swI2CInit_SM750LE(i2cClkGPIO, i2cDataGPIO);
-
/* Initialize the GPIO pin for the i2c Clock Register */
g_i2cClkGPIOMuxReg = GPIO_MUX;
g_i2cClkGPIODataReg = GPIO_DATA;
diff --git a/drivers/staging/sm750fb/sm750.c b/drivers/staging/sm750fb/sm750.c
index a7b1b9c..8a6e36b 100644
--- a/drivers/staging/sm750fb/sm750.c
+++ b/drivers/staging/sm750fb/sm750.c
@@ -701,10 +701,10 @@ static int sm750fb_set_drv(struct lynxfb_par * par)
output->proc_setMode = hw_sm750_output_setMode;
output->proc_checkMode = hw_sm750_output_checkMode;
- output->proc_setBLANK = (share->revid == SM750LE_REVISION_ID)?hw_sm750le_setBLANK:hw_sm750_setBLANK;
+ output->proc_setBLANK = hw_sm750_setBLANK;
output->clear = hw_sm750_output_clear;
/* chip specific phase */
- share->accel.de_wait = (share->revid == SM750LE_REVISION_ID)?hw_sm750le_deWait: hw_sm750_deWait;
+ share->accel.de_wait = hw_sm750_deWait;
switch (spec_share->state.dataflow)
{
case sm750_simul_pri:
@@ -1059,11 +1059,6 @@ NO_PARAM:
else
spec_share->state.dataflow = sm750_simul_pri;
}
- }else{
- /* SM750LE only have one crt channel */
- spec_share->state.dataflow = sm750_simul_sec;
- /* sm750le do not have complex attributes*/
- spec_share->state.nocrt = 0;
}
}
diff --git a/drivers/staging/sm750fb/sm750_hw.c b/drivers/staging/sm750fb/sm750_hw.c
index 9f0d06d..f7d2db9 100644
--- a/drivers/staging/sm750fb/sm750_hw.c
+++ b/drivers/staging/sm750fb/sm750_hw.c
@@ -109,9 +109,7 @@ int hw_sm750_inithw(struct lynx_share* share, struct pci_dev * pdev)
spec_share = container_of(share, struct sm750_share,share);
parm = &spec_share->state.initParm;
if(parm->chip_clk == 0)
- parm->chip_clk = (getChipType() == SM750LE)?
- DEFAULT_SM750LE_CHIP_CLOCK :
- DEFAULT_SM750_CHIP_CLOCK;
+ parm->chip_clk = DEFAULT_SM750_CHIP_CLOCK;
if(parm->mem_clk == 0)
parm->mem_clk = parm->chip_clk;
@@ -167,28 +165,6 @@ int hw_sm750_inithw(struct lynx_share* share, struct pci_dev * pdev)
spec_share->state.pnltype));
break;
}
- }else{
- /* for 750LE ,no DVI chip initilization makes Monitor no signal */
- /* Set up GPIO for software I2C to program DVI chip in the
- Xilinx SP605 board, in order to have video signal.
- */
- swI2CInit(0,1);
-
-
- /* Customer may NOT use CH7301 DVI chip, which has to be
- initialized differently.
- */
- if (swI2CReadReg(0xec, 0x4a) == 0x95)
- {
- /* The following register values for CH7301 are from
- Chrontel app note and our experiment.
- */
- pr_info("yes,CH7301 DVI chip found\n");
- swI2CWriteReg(0xec, 0x1d, 0x16);
- swI2CWriteReg(0xec, 0x21, 0x9);
- swI2CWriteReg(0xec, 0x49, 0xC0);
- pr_info("okay,CH7301 DVI chip setup done\n");
- }
}
/* init 2d engine */
@@ -247,12 +223,6 @@ int hw_sm750_output_setMode(struct lynxfb_output* output,
}
ddk750_setLogicalDispOut(dispSet);
- }else{
- /* just open DISPLAY_CONTROL_750LE register bit 3:0*/
- u32 reg;
- reg = PEEK32(DISPLAY_CONTROL_750LE);
- reg |= 0xf;
- POKE32(DISPLAY_CONTROL_750LE, reg);
}
pr_info("ddk setlogicdispout done \n");
@@ -557,25 +527,14 @@ void hw_sm750_initAccel(struct lynx_share * share)
u32 reg;
enable2DEngine(1);
- if(getChipType() == SM750LE){
- reg = PEEK32(DE_STATE1);
- reg = FIELD_SET(reg, DE_STATE1, DE_ABORT,ON);
- POKE32(DE_STATE1,reg);
-
- reg = PEEK32(DE_STATE1);
- reg = FIELD_SET(reg, DE_STATE1, DE_ABORT,OFF);
- POKE32(DE_STATE1, reg);
-
- }else{
/* engine reset */
- reg = PEEK32(SYSTEM_CTRL);
- reg = FIELD_SET(reg, SYSTEM_CTRL, DE_ABORT,ON);
- POKE32(SYSTEM_CTRL, reg);
+ reg = PEEK32(SYSTEM_CTRL);
+ reg = FIELD_SET(reg, SYSTEM_CTRL, DE_ABORT, ON);
+ POKE32(SYSTEM_CTRL, reg);
- reg = PEEK32(SYSTEM_CTRL);
- reg = FIELD_SET(reg, SYSTEM_CTRL, DE_ABORT,OFF);
- POKE32(SYSTEM_CTRL, reg);
- }
+ reg = PEEK32(SYSTEM_CTRL);
+ reg = FIELD_SET(reg, SYSTEM_CTRL, DE_ABORT, OFF);
+ POKE32(SYSTEM_CTRL, reg);
/* call 2d init */
share->accel.de_init(&share->accel);
--
1.8.1.2
--
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