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Message-Id: <1427176113-23411-1-git-send-email-zhang.chunyan@linaro.org>
Date: Tue, 24 Mar 2015 13:48:33 +0800
From: Chunyan Zhang <zhang.chunyan@...aro.org>
To: arm@...nel.org, arnd@...db.de
Cc: mathieu.poirier@...aro.org, will.deacon@....com,
mark.rutland@....com, robh+dt@...nel.org, pawel.moll@....com,
ijc+devicetree@...lion.org.uk, galak@...eaurora.org,
catalin.marinas@....com, kaixu.xia@...aro.org,
zhizhou.zhang@...eadtrum.com, orsonzhai@...il.com,
zhang.lyra@...il.com, devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: [PATCH] coresight: adding basic support for Spreadtrum SC9836
Support only for ETB, FUNNEL, STM are included currently.
Support for ETM, TPIU and the replicator linked to it are not included in
this version patch.
Signed-off-by: Chunyan Zhang <zhang.chunyan@...aro.org>
---
arch/arm64/boot/dts/sprd/sc9836.dtsi | 57 ++++++++++++++++++++++++++++++++++++
1 file changed, 57 insertions(+)
diff --git a/arch/arm64/boot/dts/sprd/sc9836.dtsi b/arch/arm64/boot/dts/sprd/sc9836.dtsi
index f92f1b4..2ca80f3 100644
--- a/arch/arm64/boot/dts/sprd/sc9836.dtsi
+++ b/arch/arm64/boot/dts/sprd/sc9836.dtsi
@@ -45,6 +45,63 @@
};
};
+ etb@...03000 {
+ compatible = "arm,coresight-etb10", "arm,primecell";
+ reg = <0 0x10003000 0 0x1000>;
+ arm,primecell-periphid = <0x0003b907>;
+ coresight-default-sink;
+ clocks = <&clk26mhz>;
+ clock-names = "apb_pclk";
+ port {
+ etb_in: endpoint {
+ slave-mode;
+ remote-endpoint = <&funnel_out_port0>;
+ };
+ };
+ };
+
+ funnel@...01000 {
+ compatible = "arm,coresight-funnel", "arm,primecell";
+ reg = <0 0x10001000 0 0x1000>;
+ clocks = <&clk26mhz>;
+ clock-names = "apb_pclk";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* funnel output port */
+ port@0 {
+ reg = <0>;
+ funnel_out_port0: endpoint {
+ remote-endpoint = <&etb_in>;
+ };
+ };
+
+ /* funnel input port 0~3 is reserved for ETMs */
+ port@1 {
+ reg = <4>;
+ funnel_in_port4: endpoint {
+ slave-mode;
+ remote-endpoint = <&stm_out>;
+ };
+ };
+ };
+ };
+
+ stm@...06000 {
+ compatible = "arm,coresight-stm", "arm,primecell";
+ reg = <0 0x10006000 0 0x1000>,
+ <0 0x01000000 0 0x180000>;
+ reg-names = "stm-base", "stm-stimulus-base";
+ clocks = <&clk26mhz>;
+ clock-names = "apb_pclk";
+ port {
+ stm_out: endpoint {
+ remote-endpoint = <&funnel_in_port4>;
+ };
+ };
+ };
+
gic: interrupt-controller@...01000 {
compatible = "arm,gic-400";
reg = <0 0x12001000 0 0x1000>,
--
1.9.1
--
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