linux-kernel - Re: [PATCH V2 1/1] X86: hyperv: Enable MSR based APIC access

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Message-ID: <20150325121514.GB2542@gmail.com>
Date:	Wed, 25 Mar 2015 13:15:14 +0100
From:	Ingo Molnar <mingo@...nel.org>
To:	"K. Y. Srinivasan" <kys@...rosoft.com>
Cc:	x86@...nel.org, gregkh@...uxfoundation.org,
	linux-kernel@...r.kernel.org, devel@...uxdriverproject.org,
	olaf@...fle.de, apw@...onical.com, jasowang@...hat.com,
	tglx@...utronix.de, hpa@...or.com
Subject: Re: [PATCH V2 1/1] X86: hyperv: Enable MSR based APIC access


* K. Y. Srinivasan <kys@...rosoft.com> wrote:

> If the hypervisor supports MSR based access to the APIC registers
> (EOI, TPR and ICR), implement the MSR based access.
> 
> Signed-off-by: K. Y. Srinivasan <kys@...rosoft.com>
> ---
>  Changes from V1: Addressed comments from Ingo Molnar <mingo.kernel.org@...il.com>

You didn't address my primary feedback:

> > So since we are trying to explain things, wouldn't this comment be 
> > more informative if it explained why we are trying to use the 
> > x2APIC facilities of Hyper-V?
> >
> > I.e. what are the benefits of using the x2apic API towards the 
> > hypervisor?

please explain the purpose, context and benefits, not just what the 
patch does - even if the comment from your first patch is now gone.

Thanks,

	Ingo
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