linux-kernel - Re: [PATCH V6 15/25] MIPS: BMIPS: Flush the readahead cache after DMA

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Message-ID: <CAJiQ=7Cca_rc+g5uo-7h6PUSu3QCbC=Ev1-hnqoqz1wy_EKeZQ@mail.gmail.com>
Date:	Wed, 25 Mar 2015 10:08:47 -0700
From:	Kevin Cernekee <cernekee@...il.com>
To:	Ralf Baechle <ralf@...ux-mips.org>
Cc:	Florian Fainelli <f.fainelli@...il.com>,
	Jaedon Shin <jaedon.shin@...il.com>,
	Andrew Bresticker <abrestic@...omium.org>,
	Thomas Gleixner <tglx@...utronix.de>,
	Jason Cooper <jason@...edaemon.net>,
	Jonas Gorski <jogo@...nwrt.org>, Arnd Bergmann <arnd@...db.de>,
	Brian Norris <computersforpeace@...il.com>,
	Linux MIPS Mailing List <linux-mips@...ux-mips.org>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH V6 15/25] MIPS: BMIPS: Flush the readahead cache after DMA

On Wed, Mar 25, 2015 at 2:23 AM, Ralf Baechle <ralf@...ux-mips.org> wrote:
> On Thu, Dec 25, 2014 at 09:49:10AM -0800, Kevin Cernekee wrote:
>
>> BMIPS 3300/435x/438x CPUs have a readahead cache that is separate from
>> the L1/L2.  During a DMA operation, accesses adjacent to a DMA buffer
>> may cause parts of the DMA buffer to be prefetched into the RAC.  To
>> avoid possible coherency problems, flush the RAC upon DMA completion.
>>
>> Signed-off-by: Kevin Cernekee <cernekee@...il.com>
>> Signed-off-by: Jaedon Shin <jaedon.shin@...il.com>
>> ---
>>  arch/mips/mm/dma-default.c | 15 +++++++++++++++
>>  1 file changed, 15 insertions(+)
>>
>> diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c
>> index af5f046..38ee47a 100644
>> --- a/arch/mips/mm/dma-default.c
>> +++ b/arch/mips/mm/dma-default.c
>> @@ -18,6 +18,7 @@
>>  #include <linux/highmem.h>
>>  #include <linux/dma-contiguous.h>
>>
>> +#include <asm/bmips.h>
>>  #include <asm/cache.h>
>>  #include <asm/cpu-type.h>
>>  #include <asm/io.h>
>
> Aside of platform-specific headers having no business of getting
> included directly in a generic arch file

<asm/bmips.h> covers all BMIPS CPUs across multiple platforms.

The intention was to add code needed to support BMIPS CPUs into a
central place, rather than duplicating it in the platform code for
each of the BMIPS-based systems: arch/mips/{bcm63xx,bmips,brcmstb}.

> this also breaks the build
> of many platforms:
>
>   CC      arch/mips/mm/dma-default.o
> In file included from arch/mips/mm/dma-default.c:21:0:
> ./arch/mips/include/asm/bmips.h: In function ‘bmips_read_zscm_reg’:
> ./arch/mips/include/asm/bmips.h:97:160: error: cast to pointer from integer of different size [-Werror=int-to-pointer-cast]
>   cache_op(Index_Load_Tag_S, ZSCM_REG_BASE + offset);
>                                                                                                                                                                 ^
> ./arch/mips/include/asm/bmips.h: In function ‘bmips_write_zscm_reg’:
> ./arch/mips/include/asm/bmips.h:118:160: error: cast to pointer from integer of different size [-Werror=int-to-pointer-cast]
>   cache_op(Index_Store_Tag_S, ZSCM_REG_BASE + offset);
>
> I think the broken platforms are all the 64 bit platforms.

Hmm, looks like I might need to use 0x97000000UL for ZSCM_REG_BASE.

If this fixes the build should I resubmit, or do you really want the
BMIPS flush code moved into another file?
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