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Message-ID: <5513CDAC.8050902@codeaurora.org>
Date: Thu, 26 Mar 2015 14:43:16 +0530
From: Rajendra Nayak <rnayak@...eaurora.org>
To: Stephane Viau <sviau@...eaurora.org>, linux-arm-msm@...r.kernel.org
CC: linux-kernel@...r.kernel.org
Subject: Re: [PATCH] clk: qcom: gdsc: Add GDSCs in apq8084 MMCC
On 03/25/2015 06:49 PM, Stephane Viau wrote:
> Add the GDSC instances that exist as part of apq8084 MMCC block.
>
> Signed-off-by: Stephane Viau <sviau@...eaurora.org>
> ---
> drivers/clk/qcom/Kconfig | 1 +
> drivers/clk/qcom/mmcc-apq8084.c | 56 ++++++++++++++++++++++++++-
> include/dt-bindings/clock/qcom,mmcc-apq8084.h | 8 ++++
> 3 files changed, 64 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> index 4dadfc9..89879e1 100644
> --- a/drivers/clk/qcom/Kconfig
> +++ b/drivers/clk/qcom/Kconfig
> @@ -15,6 +15,7 @@ config APQ_GCC_8084
> config APQ_MMCC_8084
> tristate "APQ8084 Multimedia Clock Controller"
> select APQ_GCC_8084
> + select QCOM_GDSC
> depends on COMMON_CLK_QCOM
> help
> Support for the multimedia clock controller on apq8084 devices.
> diff --git a/drivers/clk/qcom/mmcc-apq8084.c b/drivers/clk/qcom/mmcc-apq8084.c
> index 157139a..626adbd 100644
> --- a/drivers/clk/qcom/mmcc-apq8084.c
> +++ b/drivers/clk/qcom/mmcc-apq8084.c
> @@ -1,5 +1,5 @@
> /*
> - * Copyright (c) 2014, The Linux Foundation. All rights reserved.
> + * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
> *
> * This software is licensed under the terms of the GNU General Public
> * License version 2, as published by the Free Software Foundation, and
> @@ -26,6 +26,7 @@
> #include "clk-rcg.h"
> #include "clk-branch.h"
> #include "reset.h"
> +#include "gdsc.h"
>
> #define P_XO 0
> #define P_MMPLL0 1
> @@ -3075,6 +3076,48 @@ static const struct pll_config mmpll3_config = {
> .aux_output_mask = BIT(1),
> };
>
> +static struct gdsc venus0_gdsc = {
> + .gdscr = 0x1024,
> + .pd = {
> + .name = "venus0",
> + },
> +};
> +
> +static struct gdsc mdss_gdsc = {
> + .gdscr = 0x2304,
> + .pd = {
> + .name = "mdss",
> + },
> +};
> +
> +static struct gdsc camss_jpeg_gdsc = {
> + .gdscr = 0x35a4,
> + .pd = {
> + .name = "camss_jpeg",
> + },
> +};
> +
> +static struct gdsc camss_vfe_gdsc = {
> + .gdscr = 0x36a4,
> + .pd = {
> + .name = "camss_vfe",
> + },
> +};
> +
> +static struct gdsc oxili_gdsc = {
> + .gdscr = 0x4024,
> + .pd = {
> + .name = "oxili",
> + },
> +};
> +
> +static struct gdsc oxilicx_gdsc = {
> + .gdscr = 0x4034,
> + .pd = {
> + .name = "oxilicx",
> + },
> +};
> +
> static struct clk_regmap *mmcc_apq8084_clocks[] = {
> [MMSS_AHB_CLK_SRC] = &mmss_ahb_clk_src.clkr,
> [MMSS_AXI_CLK_SRC] = &mmss_axi_clk_src.clkr,
> @@ -3292,6 +3335,15 @@ static const struct qcom_reset_map mmcc_apq8084_resets[] = {
> [MMSSNOCAXI_RESET] = { 0x5060 },
> };
>
> +static struct generic_pm_domain *mmcc_apq8084_gdscs[] = {
With my v3, I changed this to an array of struct gdsc, I will
update this patch and include it in my gdsc series v4 repost, that I
will do shortly.
regards,
Rajendra
> + [VENUS0_GDSC] = &venus0_gdsc.pd,
> + [MDSS_GDSC] = &mdss_gdsc.pd,
> + [CAMSS_JPEG_GDSC] = &camss_jpeg_gdsc.pd,
> + [CAMSS_VFE_GDSC] = &camss_vfe_gdsc.pd,
> + [OXILI_GDSC] = &oxili_gdsc.pd,
> + [OXILICX_GDSC] = &oxilicx_gdsc.pd,
> +};
> +
> static const struct regmap_config mmcc_apq8084_regmap_config = {
> .reg_bits = 32,
> .reg_stride = 4,
> @@ -3306,6 +3358,8 @@ static const struct qcom_cc_desc mmcc_apq8084_desc = {
> .num_clks = ARRAY_SIZE(mmcc_apq8084_clocks),
> .resets = mmcc_apq8084_resets,
> .num_resets = ARRAY_SIZE(mmcc_apq8084_resets),
> + .gdscs = mmcc_apq8084_gdscs,
> + .num_gdscs = ARRAY_SIZE(mmcc_apq8084_gdscs),
> };
>
> static const struct of_device_id mmcc_apq8084_match_table[] = {
> diff --git a/include/dt-bindings/clock/qcom,mmcc-apq8084.h b/include/dt-bindings/clock/qcom,mmcc-apq8084.h
> index d72b5b3..21fec5d 100644
> --- a/include/dt-bindings/clock/qcom,mmcc-apq8084.h
> +++ b/include/dt-bindings/clock/qcom,mmcc-apq8084.h
> @@ -180,4 +180,12 @@
> #define VPU_SLEEP_CLK 163
> #define VPU_VDP_CLK 164
>
> +/* GDSCs */
> +#define VENUS0_GDSC 0
> +#define MDSS_GDSC 1
> +#define CAMSS_JPEG_GDSC 2
> +#define CAMSS_VFE_GDSC 3
> +#define OXILI_GDSC 4
> +#define OXILICX_GDSC 5
> +
> #endif
>
--
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