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Message-Id: <1427746633-9137-9-git-send-email-daniel.lezcano@linaro.org>
Date: Mon, 30 Mar 2015 22:17:11 +0200
From: Daniel Lezcano <daniel.lezcano@...aro.org>
To: tglx@...utronix.de, mingo@...nel.org
Cc: linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
maxime.ripard@...e-electrons.com, viresh.kumar@...aro.org,
ben.dooks@...ethink.co.uk, digetx@...il.com, hdegoede@...hat.com,
laurent.pinchart+renesas@...asonboard.com
Subject: [PATCH 09/11] clocksource: tegra: Maintain CPU endianness
From: Dmitry Osipenko <digetx@...il.com>
Support big-endian kernel by using endian-aware register access functions.
Signed-off-by: Dmitry Osipenko <digetx@...il.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@...aro.org>
Acked-by: Thierry Reding <treding@...dia.com>
---
drivers/clocksource/tegra20_timer.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clocksource/tegra20_timer.c b/drivers/clocksource/tegra20_timer.c
index d2616ef..d8a3a4e 100644
--- a/drivers/clocksource/tegra20_timer.c
+++ b/drivers/clocksource/tegra20_timer.c
@@ -57,9 +57,9 @@ static u64 persistent_ms, last_persistent_ms;
static struct delay_timer tegra_delay_timer;
#define timer_writel(value, reg) \
- __raw_writel(value, timer_reg_base + (reg))
+ writel_relaxed(value, timer_reg_base + (reg))
#define timer_readl(reg) \
- __raw_readl(timer_reg_base + (reg))
+ readl_relaxed(timer_reg_base + (reg))
static int tegra_timer_set_next_event(unsigned long cycles,
struct clock_event_device *evt)
--
1.9.1
--
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