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Message-ID: <CA+55aFxuZvO=RjMGFm9Ng3ph1oKoARK4ZHdBotHsjpbKPs6qEQ@mail.gmail.com>
Date: Wed, 1 Apr 2015 08:50:02 -0700
From: Linus Torvalds <torvalds@...ux-foundation.org>
To: Denys Vlasenko <dvlasenk@...hat.com>
Cc: Brian Gerst <brgerst@...il.com>, Ingo Molnar <mingo@...nel.org>,
Steven Rostedt <rostedt@...dmis.org>,
Borislav Petkov <bp@...en8.de>,
"H. Peter Anvin" <hpa@...or.com>,
Andy Lutomirski <luto@...capital.net>,
Oleg Nesterov <oleg@...hat.com>,
Frederic Weisbecker <fweisbec@...il.com>,
Alexei Starovoitov <ast@...mgrid.com>,
Will Drewry <wad@...omium.org>,
Kees Cook <keescook@...omium.org>,
"the arch/x86 maintainers" <x86@...nel.org>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 7/9] x86/asm/entry/32: tidy up some instructions
On Wed, Apr 1, 2015 at 4:10 AM, Denys Vlasenko <dvlasenk@...hat.com> wrote:
>
> I did not know that. I was sure they are always zero extended.
On all half-way modern cpu's they are. But on some older cpu's
(possibly just the original 386) the segment move instructions
basically are always 16-bit, and the operand size is ignored (so the
32-bit version is just smaller and faster to decode, because it
doesn't have a 16-bit operand size prefix)
Iirc, the same is true for the values pushed to memory on exceptions,
so the 'cs/ss' values on the exception stack may not be reliable in
the upper 16 bits.
I don't remember if the same might be true of "pushl %Sseg". The intel
architecture manual says segment registers are zero-extended on push.
Linus
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