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Message-ID: <CAM4voanzd-iiyTbGvZpTz4nmULJu9_VUFz3EibLB5L295K4P-Q@mail.gmail.com>
Date:	Wed, 1 Apr 2015 08:49:14 +0530
From:	Abhilash Kesavan <kesavan.abhilash@...il.com>
To:	Kevin Hilman <khilman@...nel.org>
Cc:	Javier Martinez Canillas <javier.martinez@...labora.co.uk>,
	Tomasz Figa <tomasz.figa@...il.com>,
	Stephen Boyd <sboyd@...eaurora.org>,
	Mike Turquette <mturquette@...aro.org>,
	Sylwester Nawrocki <s.nawrocki@...sung.com>,
	Kukjin Kim <kgene@...nel.org>, Olof Johansson <olof@...om.net>,
	Doug Anderson <dianders@...omium.org>,
	Krzysztof Kozlowski <k.kozlowski@...sung.com>,
	Tyler Baker <tyler.baker@...aro.org>,
	Chanwoo Choi <cw00.choi@...sung.com>,
	linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>,
	"linux-samsung-soc@...r.kernel.org" 
	<linux-samsung-soc@...r.kernel.org>,
	linux-kernel <linux-kernel@...r.kernel.org>
Subject: Re: [RFC PATCH v3 2/2] clk: exynos5420: Make sure MDMA0 clock is
 enabled during suspend

Hi Kevin,

On Wed, Apr 1, 2015 at 2:32 AM, Kevin Hilman <khilman@...nel.org> wrote:
> Javier Martinez Canillas <javier.martinez@...labora.co.uk> writes:
>
> [...]
>
>> Unfortunately I don't fully understand why this clock needs to be
>> enabled. It would be good if someone at Samsung can explain in more
>> detail what the real problem really is.
>
> +1
>
> Maybe Abhilash can shed some light here?
>
> We really should know *why* this is needed because having the fix in the
> clock driver just doesn't seem right.  It seems like the DMA driver
> should be managing this clock.

I think my last mail might not have reached you (was accidentally sent
as html). We are gating the aclk266_g2d clock without checking the
CG_STATUS0 register bits as specified in the UM. It looks like we need
to keep several clocks alive or gate them only after checking the
CG_STATUSx register bits.

Regards,
Abhilash
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