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Date:	Fri, 3 Apr 2015 20:40:46 -0700
From:	Yinghai Lu <yinghai@...nel.org>
To:	Bjorn Helgaas <bhelgaas@...gle.com>
Cc:	David Miller <davem@...emloft.net>,
	David Ahern <david.ahern@...cle.com>,
	"linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
	"sparclinux@...r.kernel.org" <sparclinux@...r.kernel.org>,
	Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
	"stable@...r.kernel.org" <stable@...r.kernel.org>
Subject: Re: [PATCH 1/3] PCI: Introduce pci_bus_addr_t

On Fri, Apr 3, 2015 at 11:59 AM, Bjorn Helgaas <bhelgaas@...gle.com> wrote:
> On Tue, Mar 31, 2015 at 07:57:47PM -0700, Yinghai Lu wrote:
>> David Ahern found commit d63e2e1f3df9 ("sparc/PCI: Clip bridge windows
>> to fit in upstream windows") broke booting on sparc/T5-8.
>>
>> In the boot log, there is
>>   pci 0000:06:00.0: reg 0x184: can't handle BAR above 4GB (bus address
>>   0x110204000)
>> but that only could happen when dma_addr_t is 32-bit.
>>
>> According to David Miller, all DMA occurs behind an IOMMU and these
>> IOMMUs only support 32-bit addressing, therefore dma_addr_t is
>> 32-bit on sparc64.
>>
>> Let's introduce pci_bus_addr_t instead of using dma_addr_t,
>> and pci_bus_addr_t will be 64-bit on 64-bit platform or X86_PAE.
>
> I propose the following doc updates (I can just fold them into this patch
> if you approve):
>
>
> commit 13fca18e2f1d9dd078b8dfea965718cf13a4b600
> Author: Bjorn Helgaas <bhelgaas@...gle.com>
> Date:   Fri Apr 3 12:39:35 2015 -0500
>
>     pci-bus-addr-fixups
>
> diff --git a/include/linux/types.h b/include/linux/types.h
> index 6747247e3f9f..00a127e89752 100644
> --- a/include/linux/types.h
> +++ b/include/linux/types.h
> @@ -139,12 +139,20 @@ typedef unsigned long blkcnt_t;
>   */
>  #define pgoff_t unsigned long
>
> -/* A dma_addr_t can hold any valid DMA or bus address for the platform */
> +/*
> + * A dma_addr_t can hold any valid DMA address, i.e., any address returned
> + * by the DMA API.
> + *
> + * If the DMA API only uses 32-bit addresses, dma_addr_t need only be 32
> + * bits wide.  Bus addresses, e.g., PCI BARs, may be wider than 32 bits,
> + * but drivers do memory-mapped I/O to ioremapped kernel virtual addresses,
> + * so they don't care about the size of the actual bus addresses.
> + */

Good to me.

Thanks

Yinghai
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