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Message-Id: <1428345067-21878-6-git-send-email-sricharan@codeaurora.org>
Date: Tue, 7 Apr 2015 00:01:06 +0530
From: Sricharan R <sricharan@...eaurora.org>
To: devicetree@...r.kernel.org, linux-arm-msm@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, dmaengine@...r.kernel.org,
galak@...eaurora.org, linux-i2c@...r.kernel.org,
linux-kernel@...r.kernel.org, agross@...eaurora.org,
iivanov@...sol.com
Cc: srichara@....qualcomm.com
Subject: [PATCH V2 5/6] dts: msm8974: Add blsp2_bam dma node
Signed-off-by: Sricharan R <sricharan@...eaurora.org>
---
[v2] Used macros for interrupts property.
arch/arm/boot/dts/qcom-msm8974.dtsi | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
index 2d11641..c2e8711 100644
--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
@@ -1,6 +1,6 @@
/dts-v1/;
-#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-msm8974.h>
#include "skeleton.dtsi"
@@ -263,5 +263,15 @@
interrupt-controller;
#interrupt-cells = <4>;
};
+
+ blsp2_dma: dma@...44000 {
+ compatible = "qcom,bam-v1.4.0";
+ reg = <0xf9944000 0x19000>;
+ interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP2_AHB_CLK>;
+ clock-names = "bam_clk";
+ #dma-cells = <1>;
+ qcom,ee = <0>;
+ };
};
};
--
1.8.2.1
--
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