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Message-ID: <1428392854-3228-2-git-send-email-thunder.leizhen@huawei.com>
Date:	Tue, 7 Apr 2015 15:47:33 +0800
From:	Zhen Lei <thunder.leizhen@...wei.com>
To:	Thomas Gleixner <tglx@...utronix.de>,
	Jason Cooper <jason@...edaemon.net>,
	Marc Zyngier <marc.zyngier@....com>,
	linux-kernel <linux-kernel@...r.kernel.org>
CC:	Zefan Li <lizefan@...wei.com>, Xinwei Hu <huxinwei@...wei.com>,
	"Tianhong Ding" <dingtianhong@...wei.com>,
	Kefeng Wang <wangkefeng.wang@...wei.com>,
	"Yun Wu" <wuyun.wu@...wei.com>,
	Zhen Lei <thunder.leizhen@...wei.com>
Subject: [PATCH 2/3] irqchip/gicv3-its: remove GITS_BASER_TYPE_CPU base on latest spec

In the latest specification(version 24.0), clause 5.12.13 GITS_BASERn.
The meaning of value=0x3 in "Type" field was revised to reserved. As
below:
0x3. Reserved.

In the early versions(like 19.0), it defined as below:
0x3. Physical Processors.

Signed-off-by: Zhen Lei <thunder.leizhen@...wei.com>
---
 drivers/irqchip/irq-gic-v3-its.c   | 2 +-
 include/linux/irqchip/arm-gic-v3.h | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index 2577f06..bbf9504 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -777,7 +777,7 @@ static int __init its_alloc_lpi_tables(void)
 static const char *its_base_type_string[] = {
 	[GITS_BASER_TYPE_DEVICE]	= "Devices",
 	[GITS_BASER_TYPE_VCPU]		= "Virtual CPUs",
-	[GITS_BASER_TYPE_CPU]		= "Physical CPUs",
+	[GITS_BASER_TYPE_RESERVED3]	= "Reserved (3)",
 	[GITS_BASER_TYPE_COLLECTION]	= "Interrupt Collections",
 	[GITS_BASER_TYPE_RESERVED5] 	= "Reserved (5)",
 	[GITS_BASER_TYPE_RESERVED6] 	= "Reserved (6)",
diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h
index ffbc034..67f5779 100644
--- a/include/linux/irqchip/arm-gic-v3.h
+++ b/include/linux/irqchip/arm-gic-v3.h
@@ -233,7 +233,7 @@
 #define GITS_BASER_TYPE_NONE		0
 #define GITS_BASER_TYPE_DEVICE		1
 #define GITS_BASER_TYPE_VCPU		2
-#define GITS_BASER_TYPE_CPU		3
+#define GITS_BASER_TYPE_RESERVED3	3
 #define GITS_BASER_TYPE_COLLECTION	4
 #define GITS_BASER_TYPE_RESERVED5	5
 #define GITS_BASER_TYPE_RESERVED6	6
--
1.8.0


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