linux-kernel - Re: [RFC PATCH v3 2/2] clk: exynos5420: Make sure MDMA0 clock is enabled during suspend

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Date:	Tue, 07 Apr 2015 17:00:29 +0200
From:	Javier Martinez Canillas <javier.martinez@...labora.co.uk>
To:	Abhilash Kesavan <kesavan.abhilash@...il.com>
CC:	Tomasz Figa <tomasz.figa@...il.com>,
	Sylwester Nawrocki <s.nawrocki@...sung.com>,
	Stephen Boyd <sboyd@...eaurora.org>,
	Mike Turquette <mturquette@...aro.org>,
	Kukjin Kim <kgene@...nel.org>, Olof Johansson <olof@...om.net>,
	Doug Anderson <dianders@...omium.org>,
	Krzysztof Kozlowski <k.kozlowski@...sung.com>,
	Kevin Hilman <khilman@...aro.org>,
	Tyler Baker <tyler.baker@...aro.org>,
	Chanwoo Choi <cw00.choi@...sung.com>,
	linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>,
	"linux-samsung-soc@...r.kernel.org" 
	<linux-samsung-soc@...r.kernel.org>,
	linux-kernel <linux-kernel@...r.kernel.org>
Subject: Re: [RFC PATCH v3 2/2] clk: exynos5420: Make sure MDMA0 clock is
 enabled during suspend

Hello Abhilash,

On 04/07/2015 04:38 PM, Abhilash Kesavan wrote:
>>
>> [0]
>> From 78aa551ebcb9a4a7ae9d5581c33e0c0f19fe5ad6 Mon Sep 17 00:00:00 2001
>> From: Javier Martinez Canillas <javier.martinez@...labora.co.uk>
>> Date: Tue, 7 Apr 2015 15:53:27 +0200
>> Subject: [RFC PATCH] clk: exynos5420: Restore GATE_BUS_TOP on suspend
>>
>> Commit ae43b3289186 ("ARM: 8202/1: dmaengine: pl330: Add runtime Power
>> Management support v12") added pm support for the pl330 dma driver but
>> it makes the clock for the Exynos5420 MDMA0 DMA controller to be gated
>> during suspend and this in turn makes its parent clock aclk266_g2d to
>> be gated. But the clock needs to be ungated prior suspend to allow the
>> system to be suspend and resumed correctly.
>>
>> Add GATE_BUS_TOP register to the list of registers to be restored when
>> the system enters into a suspend state so aclk266_g2d will be ungated.
>>
>> Thanks to Abhilash Kesavan for figuring out that this was the issue.
>>
>> Fixes: ae43b32 ("ARM: 8202/1: dmaengine: pl330: Add runtime Power Management support v12")
>> Signed-off-by: Javier Martinez Canillas <javier.martinez@...labora.co.uk>
>> ---
>>  drivers/clk/samsung/clk-exynos5420.c | 1 +
>>  1 file changed, 1 insertion(+)
>>
>> diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
>> index 07d666cc6a29..bea4a173eef5 100644
>> --- a/drivers/clk/samsung/clk-exynos5420.c
>> +++ b/drivers/clk/samsung/clk-exynos5420.c
>> @@ -271,6 +271,7 @@ static const struct samsung_clk_reg_dump exynos5420_set_clksrc[] = {
>>         { .offset = SRC_MASK_PERIC0,            .value = 0x11111110, },
>>         { .offset = SRC_MASK_PERIC1,            .value = 0x11111100, },
>>         { .offset = SRC_MASK_ISP,               .value = 0x11111000, },
>> +       { .offset = GATE_BUS_TOP,               .value = 0xffffffff, },
>>         { .offset = GATE_BUS_DISP1,             .value = 0xffffffff, },
>>         { .offset = GATE_IP_PERIC,              .value = 0xffffffff, },
>>  };
> 
> While there could be a concern that we are ungating all the clocks in

Yes, I mentioned that but OTOH it will be even more dangerous to gate
clocks that should remain enabled so I used the register default values.

> BUS_TOP, this looks like the least intrusive fix for the issue. Tested
> this on Peach Pi, S2R works fine.
>

Thanks a lot for testing, does it mean I can add your Tested-by then when
posting it as a proper patch? I'll wait for Tomasz to comment before though.
 
> Thanks,
> Abhilash
> 

Best regards,
Javier
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