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Message-ID: <55256899.4040603@hp.com>
Date:	Wed, 08 Apr 2015 13:42:49 -0400
From:	Waiman Long <waiman.long@...com>
To:	David Vrabel <david.vrabel@...rix.com>
CC:	Thomas Gleixner <tglx@...utronix.de>,
	Ingo Molnar <mingo@...hat.com>,
	"H. Peter Anvin" <hpa@...or.com>,
	Peter Zijlstra <peterz@...radead.org>,
	linux-arch@...r.kernel.org, Rik van Riel <riel@...hat.com>,
	Raghavendra K T <raghavendra.kt@...ux.vnet.ibm.com>,
	kvm@...r.kernel.org, Daniel J Blueman <daniel@...ascale.com>,
	x86@...nel.org, Paolo Bonzini <paolo.bonzini@...il.com>,
	linux-kernel@...r.kernel.org,
	virtualization@...ts.linux-foundation.org,
	Scott J Norton <scott.norton@...com>,
	Oleg Nesterov <oleg@...hat.com>,
	xen-devel@...ts.xenproject.org,
	Boris Ostrovsky <boris.ostrovsky@...cle.com>,
	"Paul E. McKenney" <paulmck@...ux.vnet.ibm.com>,
	Linus Torvalds <torvalds@...ux-foundation.org>,
	Douglas Hatch <doug.hatch@...com>
Subject: Re: [Xen-devel] [PATCH v15 12/15] pvqspinlock, x86: Enable PV qspinlock
 for Xen

On 04/08/2015 08:01 AM, David Vrabel wrote:
> On 07/04/15 03:55, Waiman Long wrote:
>> This patch adds the necessary Xen specific code to allow Xen to
>> support the CPU halting and kicking operations needed by the queue
>> spinlock PV code.
> This basically looks the same as the version I wrote, except I think you
> broke it.
>
>> +static void xen_qlock_wait(u8 *byte, u8 val)
>> +{
>> +	int irq = __this_cpu_read(lock_kicker_irq);
>> +
>> +	/* If kicker interrupts not initialized yet, just spin */
>> +	if (irq == -1)
>> +		return;
>> +
>> +	/* clear pending */
>> +	xen_clear_irq_pending(irq);
>> +
>> +	/*
>> +	 * We check the byte value after clearing pending IRQ to make sure
>> +	 * that we won't miss a wakeup event because of the clearing.
> My version had a barrier() here to ensure this.  The documentation of
> READ_ONCE() suggests that it is not sufficient to meet this requirement
> (and a READ_ONCE() here is not required anyway).

I have the misconception that a READ_ONCE/WRITE_ONCE() implies a 
compiler barrier. You are right that it may not be the case. I will add 
back the missing barrier when I update the patch and add you as the 
author of this patch if you don't mind.

Cheers,
Longman
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