linux-kernel - Re: [PATCH] x86: Align jump targets to 1 byte boundaries

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Message-ID: <20150410140141.GI28074@pd.tnic>
Date:	Fri, 10 Apr 2015 16:01:41 +0200
From:	Borislav Petkov <bp@...en8.de>
To:	Denys Vlasenko <dvlasenk@...hat.com>
Cc:	Ingo Molnar <mingo@...nel.org>,
	"Paul E. McKenney" <paulmck@...ux.vnet.ibm.com>,
	Linus Torvalds <torvalds@...ux-foundation.org>,
	Jason Low <jason.low2@...com>,
	Peter Zijlstra <peterz@...radead.org>,
	Davidlohr Bueso <dave@...olabs.net>,
	Tim Chen <tim.c.chen@...ux.intel.com>,
	Aswin Chandramouleeswaran <aswin@...com>,
	LKML <linux-kernel@...r.kernel.org>,
	Andy Lutomirski <luto@...capital.net>,
	Brian Gerst <brgerst@...il.com>,
	"H. Peter Anvin" <hpa@...or.com>,
	Thomas Gleixner <tglx@...utronix.de>,
	Peter Zijlstra <a.p.zijlstra@...llo.nl>
Subject: Re: [PATCH] x86: Align jump targets to 1 byte boundaries

On Fri, Apr 10, 2015 at 03:54:57PM +0200, Denys Vlasenko wrote:
> On 04/10/2015 03:19 PM, Borislav Petkov wrote:
> > On Fri, Apr 10, 2015 at 02:08:46PM +0200, Ingo Molnar wrote:
> >> Now, the usual justification for jump target alignment is the 
> >> following: with 16 byte instruction-cache cacheline sizes, if a 
> > 
> > You mean 64 bytes?
> > 
> > Cacheline size on modern x86 is 64 bytes. The 16 alignment is probably
> > some branch predictor stride thing.
> 
> IIRC it's a maximum decode bandwidth. Decoders on the most powerful
> x86 CPUs, both Intel and AMD, attempt to decode in one cycle
> up to four instructions. For this they fetch up to 16 bytes.

32 bytes fetch window per cycle for AMD F15h and F16h, see my other
mail. And Intel probably do the same.

> If cacheline ends before 16 bytes are available, then decode
> will operate on fewer bytes, or it will wait for next cacheline
> to be fetched.

Yap.

-- 
Regards/Gruss,
    Boris.

ECO tip #101: Trim your mails when you reply.
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