lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
Open Source and information security mailing list archives
| ||
|
Date: Fri, 10 Apr 2015 14:46:13 -0700 From: Andy Lutomirski <luto@...capital.net> To: Andi Kleen <andi@...stfloor.org> Cc: X86 ML <x86@...nel.org>, Andrew Lutomirski <luto@...nel.org>, "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>, Andi Kleen <ak@...ux.intel.com> Subject: Re: [PATCH 5/8] x86: Make old K8 swapgs workaround conditional On Fri, Apr 10, 2015 at 8:50 AM, Andi Kleen <andi@...stfloor.org> wrote: > From: Andi Kleen <ak@...ux.intel.com> > > Every gs selector/index reload always paid an extra MFENCE > between the two SWAPGS. This was to work around an old > bug in early K8 steppings. All other CPUs don't need the extra > mfence. Patch the extra MFENCE only in for K8. > > Signed-off-by: Andi Kleen <ak@...ux.intel.com> > --- > arch/x86/include/asm/cpufeature.h | 1 + > arch/x86/kernel/cpu/amd.c | 3 +++ > arch/x86/kernel/entry_64.S | 10 +++++++++- > 3 files changed, 13 insertions(+), 1 deletion(-) > > diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h > index 90a5485..c695fad 100644 > --- a/arch/x86/include/asm/cpufeature.h > +++ b/arch/x86/include/asm/cpufeature.h > @@ -255,6 +255,7 @@ > #define X86_BUG_11AP X86_BUG(5) /* Bad local APIC aka 11AP */ > #define X86_BUG_FXSAVE_LEAK X86_BUG(6) /* FXSAVE leaks FOP/FIP/FOP */ > #define X86_BUG_CLFLUSH_MONITOR X86_BUG(7) /* AAI65, CLFLUSH required before MONITOR */ > +#define X86_BUG_SWAPGS_MFENCE X86_BUG(8) /* SWAPGS may need MFENCE */ > > #if defined(__KERNEL__) && !defined(__ASSEMBLY__) > > diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c > index a220239..e7f5667 100644 > --- a/arch/x86/kernel/cpu/amd.c > +++ b/arch/x86/kernel/cpu/amd.c > @@ -551,6 +551,9 @@ static void init_amd_k8(struct cpuinfo_x86 *c) > if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58) > set_cpu_cap(c, X86_FEATURE_REP_GOOD); > > + /* Early steppings needed a mfence on swapgs. */ > + set_cpu_cap(c, X86_BUG_SWAPGS_MFENCE); > + > /* > * Some BIOSes incorrectly force this feature, but only K8 revision D > * (model = 0x14) and later actually support it. > diff --git a/arch/x86/kernel/entry_64.S b/arch/x86/kernel/entry_64.S > index 0b74ab0..bb44292 100644 > --- a/arch/x86/kernel/entry_64.S > +++ b/arch/x86/kernel/entry_64.S > @@ -1212,13 +1212,21 @@ ENTRY(native_load_gs_index) > SWAPGS > gs_change: > movl %edi,%gs > -2: mfence /* workaround */ > +2: ASM_NOP3 /* may be replaced with mfence */ ALTERNATIVE, please. --Andy -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@...r.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Powered by blists - more mailing lists