linux-kernel - Re: [PATCH v4 1/4] PCI: X-Gene: Add the APM X-Gene v1 PCIe MSI/MSIX termination driver

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Message-ID: <2940382.sQOGMMprLX@wuerfel>
Date:	Tue, 21 Apr 2015 09:16:49 +0200
From:	Arnd Bergmann <arnd@...db.de>
To:	linux-arm-kernel@...ts.infradead.org
Cc:	Feng Kan <fkan@....com>, Marc Zyngier <marc.zyngier@....com>,
	linux-pci@...r.kernel.org, Duc Dang <dhdang@....com>,
	Liviu Dudau <Liviu.Dudau@....com>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	Bjorn Helgaas <bhelgaas@...gle.com>,
	Tanmay Inamdar <tinamdar@....com>,
	Grant Likely <grant.likely@...aro.org>, Loc Ho <lho@....com>
Subject: Re: [PATCH v4 1/4] PCI: X-Gene: Add the APM X-Gene v1 PCIe MSI/MSIX termination driver

On Monday 20 April 2015 11:49:37 Feng Kan wrote:
> >
> > Obviously they appear on the PCI host bridge in order, because that
> > is a how PCI works. My question was about what happens then. On a lot
> > of SoCs, there is something like an AXI bus that uses posted
> > transactions between PCI and RAM, so you have a do a full manual
> > syncronization of ongoing PIC DMAs when the MSI catcher signals the
> > top-level interrupt. Do you have a bus between PCI and RAM that does
> > not require this, or does the MSI catcher have logic to flush all DMAs?
> 
> Our hardware has an automatic mechanism to flush the content to DRAM before the
> MSI write is committed.

Ok, excellent!

	Arnd
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