linux-kernel - [tip:x86/urgent] perf/x86/intel/uncore: Add support for Intel Haswell ULT (lower power Mobile Processor) IMC uncore PMUs

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Message-ID: <tip-5324e72e00012126101aee6f3e62977055a3b5ee@git.kernel.org>
Date:	Tue, 21 Apr 2015 00:33:38 -0700
From:	tip-bot for Sonny Rao <tipbot@...or.com>
To:	linux-tip-commits@...r.kernel.org
Cc:	a.p.zijlstra@...llo.nl, linux-kernel@...r.kernel.org,
	bhelgaas@...gle.com, eranian@...gle.com, paulus@...ba.org,
	sonnyrao@...omium.org, mingo@...nel.org, tglx@...utronix.de,
	acme@...nel.org, hpa@...or.com
Subject: [tip:x86/urgent] perf/x86/intel/uncore:
  Add support for Intel Haswell ULT (lower power Mobile Processor)
  IMC uncore PMUs

Commit-ID:  5324e72e00012126101aee6f3e62977055a3b5ee
Gitweb:     http://git.kernel.org/tip/5324e72e00012126101aee6f3e62977055a3b5ee
Author:     Sonny Rao <sonnyrao@...omium.org>
AuthorDate: Mon, 20 Apr 2015 15:34:07 -0700
Committer:  Ingo Molnar <mingo@...nel.org>
CommitDate: Tue, 21 Apr 2015 09:31:17 +0200

perf/x86/intel/uncore: Add support for Intel Haswell ULT (lower power Mobile Processor) IMC uncore PMUs

This uncore is the same as the Haswell desktop part but uses a
different PCI ID.

Signed-off-by: Sonny Rao <sonnyrao@...omium.org>
Cc: Arnaldo Carvalho de Melo <acme@...nel.org>
Cc: Bjorn Helgaas <bhelgaas@...gle.com>
Cc: Paul Mackerras <paulus@...ba.org>
Cc: Peter Zijlstra <a.p.zijlstra@...llo.nl>
Cc: Stephane Eranian <eranian@...gle.com>
Link: http://lkml.kernel.org/r/1429569247-16697-1-git-send-email-sonnyrao@chromium.org
Signed-off-by: Ingo Molnar <mingo@...nel.org>
---
 arch/x86/kernel/cpu/perf_event_intel_uncore_snb.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/x86/kernel/cpu/perf_event_intel_uncore_snb.c b/arch/x86/kernel/cpu/perf_event_intel_uncore_snb.c
index 3001015..ca75e70 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_uncore_snb.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_uncore_snb.c
@@ -1,6 +1,9 @@
 /* Nehalem/SandBridge/Haswell uncore support */
 #include "perf_event_intel_uncore.h"
 
+/* Uncore IMC PCI Id */
+#define PCI_DEVICE_ID_INTEL_HSW_U_IMC	0x0a04
+
 /* SNB event control */
 #define SNB_UNC_CTL_EV_SEL_MASK			0x000000ff
 #define SNB_UNC_CTL_UMASK_MASK			0x0000ff00
@@ -472,6 +475,10 @@ static const struct pci_device_id hsw_uncore_pci_ids[] = {
 		PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HSW_IMC),
 		.driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
 	},
+	{ /* IMC */
+		PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HSW_U_IMC),
+		.driver_data = UNCORE_PCI_DEV_DATA(SNB_PCI_UNCORE_IMC, 0),
+	},
 	{ /* end: all zeroes */ },
 };
 
@@ -502,6 +509,7 @@ static const struct imc_uncore_pci_dev desktop_imc_pci_ids[] = {
 	IMC_DEV(IVB_IMC, &ivb_uncore_pci_driver),    /* 3rd Gen Core processor */
 	IMC_DEV(IVB_E3_IMC, &ivb_uncore_pci_driver), /* Xeon E3-1200 v2/3rd Gen Core processor */
 	IMC_DEV(HSW_IMC, &hsw_uncore_pci_driver),    /* 4th Gen Core Processor */
+	IMC_DEV(HSW_U_IMC, &hsw_uncore_pci_driver),  /* 4th Gen Core ULT Mobile Processor */
 	{  /* end marker */ }
 };
 
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