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Message-ID: <alpine.DEB.2.11.1504232153080.13914@nanos>
Date: Thu, 23 Apr 2015 22:01:04 +0200 (CEST)
From: Thomas Gleixner <tglx@...utronix.de>
To: Alexander Shishkin <alexander.shishkin@...ux.intel.com>
cc: Ingo Molnar <mingo@...hat.com>, "H. Peter Anvin" <hpa@...or.com>,
x86@...nel.org, Don Zickus <dzickus@...hat.com>,
Frederic Weisbecker <fweisbec@...il.com>,
Andi Kleen <ak@...ux.intel.com>,
Adrian Hunter <adrian.hunter@...el.com>,
Anton Blanchard <anton@...ba.org>,
Michael Ellerman <mpe@...erman.id.au>,
linux-kernel@...r.kernel.org, stable@...r.kernel.org
Subject: Re: [PATCH v1] watchdog: Use a reference cycle counter to avoid
scaling issues
On Thu, 23 Apr 2015, Alexander Shishkin wrote:
> The problem with using cycle counter for NMI watchdog is that its
> frequency changes with the corresponding core's frequency. This means
> that, in particular, if the core frequency scales up, watchdog NMI will
> arrive more frequently than what user requested through watchdog_thresh
> and also increasing the probability of setting off the hardlockup detector,
> because the corresponding hrtimer will keep firing at the same intervals
> regardless of the core frequency. And, if the core can turbo to up to 2.5x
> its base frequency (and therefore TSC) [1], we'll have the hrtimer and NMI
So you are saying that this M-5Y10 has a non-constant TSC again? You
really can't be serious about that.
Please provide the output of /proc/cpuinfo
Thanks,
tglx
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