linux-kernel - [tip:x86/apic] x86/irq: Introduce helper functions to support hierarchical irqdomains for IOAPIC

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Date:	Fri, 24 Apr 2015 08:53:56 -0700
From:	tip-bot for Jiang Liu <tipbot@...or.com>
To:	linux-tip-commits@...r.kernel.org
Cc:	jiang.liu@...ux.intel.com, tglx@...utronix.de, joro@...tes.org,
	linux-kernel@...r.kernel.org, hpa@...or.com, rdunlap@...radead.org,
	jroedel@...e.de, benh@...nel.crashing.org,
	gregkh@...uxfoundation.org, yinghai@...nel.org,
	bhelgaas@...gle.com, rjw@...ysocki.net,
	david.a.cohen@...ux.intel.com, bp@...en8.de,
	david.vrabel@...rix.com, konrad.wilk@...cle.com, sivanich@....com,
	mingo@...nel.org, tony.luck@...el.com, grant.likely@...aro.org,
	linux@...elenboom.it
Subject: [tip:x86/apic] x86/irq:
  Introduce helper functions to support hierarchical irqdomains for IOAPIC

Commit-ID:  96ed44b2d5e0e9d6e5b135e84ea5c8cd763ce861
Gitweb:     http://git.kernel.org/tip/96ed44b2d5e0e9d6e5b135e84ea5c8cd763ce861
Author:     Jiang Liu <jiang.liu@...ux.intel.com>
AuthorDate: Mon, 13 Apr 2015 14:11:58 +0800
Committer:  Thomas Gleixner <tglx@...utronix.de>
CommitDate: Fri, 24 Apr 2015 15:36:51 +0200

x86/irq: Introduce helper functions to support hierarchical irqdomains for IOAPIC

Introduce several helper functions, which will be used to enable
hierarchical irqdomain for IOAPIC.

Signed-off-by: Jiang Liu <jiang.liu@...ux.intel.com>
Tested-by: Joerg Roedel <jroedel@...e.de>
Cc: Konrad Rzeszutek Wilk <konrad.wilk@...cle.com>
Cc: David Cohen <david.a.cohen@...ux.intel.com>
Cc: Sander Eikelenboom <linux@...elenboom.it>
Cc: David Vrabel <david.vrabel@...rix.com>
Cc: Tony Luck <tony.luck@...el.com>
Cc: Joerg Roedel <joro@...tes.org>
Cc: Greg Kroah-Hartman <gregkh@...uxfoundation.org>
Cc: Bjorn Helgaas <bhelgaas@...gle.com>
Cc: Benjamin Herrenschmidt <benh@...nel.crashing.org>
Cc: Rafael J. Wysocki <rjw@...ysocki.net>
Cc: Randy Dunlap <rdunlap@...radead.org>
Cc: Yinghai Lu <yinghai@...nel.org>
Cc: Borislav Petkov <bp@...en8.de>
Cc: Dimitri Sivanich <sivanich@....com>
Cc: Grant Likely <grant.likely@...aro.org>
Link: http://lkml.kernel.org/r/1428905519-23704-37-git-send-email-jiang.liu@linux.intel.com
Signed-off-by: Thomas Gleixner <tglx@...utronix.de>
---
 arch/x86/kernel/apic/io_apic.c | 61 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 61 insertions(+)

diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c
index 3c66096..c8f786b 100644
--- a/arch/x86/kernel/apic/io_apic.c
+++ b/arch/x86/kernel/apic/io_apic.c
@@ -82,6 +82,7 @@ struct mp_chip_data {
 	struct IO_APIC_route_entry entry;
 	int trigger;
 	int polarity;
+	u32 count;
 	bool isa_irq;
 };
 
@@ -945,6 +946,46 @@ void ioapic_set_alloc_attr(struct irq_alloc_info *info, int node,
 	info->ioapic_valid = 1;
 }
 
+#ifndef CONFIG_ACPI
+int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity);
+#endif
+
+static void ioapic_copy_alloc_attr(struct irq_alloc_info *dst,
+				   struct irq_alloc_info *src,
+				   u32 gsi, int ioapic_idx, int pin)
+{
+	int trigger, polarity;
+
+	copy_irq_alloc_info(dst, src);
+	dst->type = X86_IRQ_ALLOC_TYPE_IOAPIC;
+	dst->ioapic_id = mpc_ioapic_id(ioapic_idx);
+	dst->ioapic_pin = pin;
+	dst->ioapic_valid = 1;
+	if (src && src->ioapic_valid) {
+		dst->ioapic_node = src->ioapic_node;
+		dst->ioapic_trigger = src->ioapic_trigger;
+		dst->ioapic_polarity = src->ioapic_polarity;
+	} else {
+		dst->ioapic_node = NUMA_NO_NODE;
+		if (acpi_get_override_irq(gsi, &trigger, &polarity) >= 0) {
+			dst->ioapic_trigger = trigger;
+			dst->ioapic_polarity = polarity;
+		} else {
+			/*
+			 * PCI interrupts are always polarity one level
+			 * triggered.
+			 */
+			dst->ioapic_trigger = 1;
+			dst->ioapic_polarity = 1;
+		}
+	}
+}
+
+static int ioapic_alloc_attr_node(struct irq_alloc_info *info)
+{
+	return (info && info->ioapic_valid) ? info->ioapic_node : NUMA_NO_NODE;
+}
+
 static void mp_register_handler(unsigned int irq, unsigned long trigger)
 {
 	irq_flow_handler_t hdl;
@@ -962,6 +1003,26 @@ static void mp_register_handler(unsigned int irq, unsigned long trigger)
 	__irq_set_handler(irq, hdl, 0, fasteoi ? "fasteoi" : "edge");
 }
 
+static bool mp_check_pin_attr(int irq, struct irq_alloc_info *info)
+{
+	struct mp_chip_data *data = irq_get_chip_data(irq);
+
+	/*
+	 * setup_IO_APIC_irqs() programs all legacy IRQs with default trigger
+	 * and polarity attirbutes. So allow the first user to reprogram the
+	 * pin with real trigger and polarity attributes.
+	 */
+	if (irq < nr_legacy_irqs() && data->count == 1) {
+		if (info->ioapic_trigger != data->trigger)
+			mp_register_handler(irq, data->trigger);
+		data->entry.trigger = data->trigger = info->ioapic_trigger;
+		data->entry.polarity = data->polarity = info->ioapic_polarity;
+	}
+
+	return data->trigger == info->ioapic_trigger &&
+	       data->polarity == info->ioapic_polarity;
+}
+
 static int alloc_irq_from_domain(struct irq_domain *domain, u32 gsi, int pin,
 				 struct irq_alloc_info *info)
 {
--
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