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Message-ID: <CAL1qeaHnKDOrmPFuh8=K8Y+r0Ff-0XKu8c1=ecX=Ud+Qk_8dkw@mail.gmail.com>
Date: Tue, 28 Apr 2015 15:56:24 -0700
From: Andrew Bresticker <abrestic@...omium.org>
To: Ezequiel Garcia <ezequiel.garcia@...tec.com>
Cc: Linus Walleij <linus.walleij@...aro.org>,
Alexandre Courbot <gnurou@...il.com>,
Ralf Baechle <ralf@...ux-mips.org>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"linux-gpio@...r.kernel.org" <linux-gpio@...r.kernel.org>,
Linux-MIPS <linux-mips@...ux-mips.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
James Hartley <james.hartley@...tec.com>,
James Hogan <james.hogan@...tec.com>,
Damien Horsley <Damien.Horsley@...tec.com>,
Govindraj Raja <govindraj.raja@...tec.com>,
Kevin Cernekee <cernekee@...omium.org>,
Paul Bolle <pebolle@...cali.nl>
Subject: Re: [PATCH V3 2/2] pinctrl: Add Pistachio SoC pin control driver
On Tue, Apr 28, 2015 at 3:40 PM, Ezequiel Garcia
<ezequiel.garcia@...tec.com> wrote:
> Just a silly comment.
>
> On 04/07/2015 04:44 PM, Andrew Bresticker wrote:
> [..]
>> +
>> +static const struct pinmux_ops pistachio_pinmux_ops = {
>> + .get_functions_count = pistachio_pinmux_get_functions_count,
>> + .get_function_name = pistachio_pinmux_get_function_name,
>> + .get_function_groups = pistachio_pinmux_get_function_groups,
>> + .set_mux = pistachio_pinmux_enable,
>> +};
>> +
>> +static int pistachio_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,
>> + unsigned long *config)
>> +{
>> + struct pistachio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
>> + enum pin_config_param param = pinconf_to_config_param(*config);
>> + u32 val, arg;
>> +
>> + switch (param) {
>> + case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
>> + val = pctl_readl(pctl, PADS_SCHMITT_EN_REG(pin));
>> + arg = !!(val & PADS_SCHMITT_EN_BIT(pin));
>> + break;
>> + case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
>> + val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >>
>> + PADS_PU_PD_SHIFT(pin);
>> + arg = (val & PADS_PU_PD_MASK) == PADS_PU_PD_HIGHZ;
>> + break;
>> + case PIN_CONFIG_BIAS_PULL_UP:
>> + val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >>
>> + PADS_PU_PD_SHIFT(pin);
>> + arg = (val & PADS_PU_PD_MASK) == PADS_PU_PD_UP;
>> + break;
>> + case PIN_CONFIG_BIAS_PULL_DOWN:
>> + val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >>
>> + PADS_PU_PD_SHIFT(pin);
>> + arg = (val & PADS_PU_PD_MASK) == PADS_PU_PD_DOWN;
>> + break;
>> + case PIN_CONFIG_BIAS_BUS_HOLD:
>> + val = pctl_readl(pctl, PADS_PU_PD_REG(pin)) >>
>> + PADS_PU_PD_SHIFT(pin);
>> + arg = (val & PADS_PU_PD_MASK) == PADS_PU_PD_BUS;
>> + break;
>> + case PIN_CONFIG_SLEW_RATE:
>> + val = pctl_readl(pctl, PADS_SLEW_RATE_REG(pin));
>> + arg = !!(val & PADS_SLEW_RATE_BIT(pin));
>> + break;
>> + case PIN_CONFIG_DRIVE_STRENGTH:
>> + val = pctl_readl(pctl, PADS_DRIVE_STRENGTH_REG(pin)) >>
>> + PADS_DRIVE_STRENGTH_SHIFT(pin);
>> + switch (val & PADS_DRIVE_STRENGTH_MASK) {
>> + case PADS_DRIVE_STRENGTH_2MA:
>> + arg = 2;
>> + break;
>> + case PADS_DRIVE_STRENGTH_4MA:
>> + arg = 4;
>> + break;
>> + case PADS_DRIVE_STRENGTH_8MA:
>> + arg = 8;
>> + break;
>> + case PADS_DRIVE_STRENGTH_12MA:
>> + default:
>> + arg = 12;
>> + break;
>> + }
>> + break;
>> + default:
>> + dev_err(pctl->dev, "Property %u not supported\n", param);
>
> Probably just a nitpick, but maybe this should be dev_dbg. Otherwise,
> we'll get a ton of these errors when cat'ing pinconf-pins in debugfs.
>
>> + return -EINVAL;
>
> And this should be -ENOTSUPP. I guess it doesn't matter much.
Ah, you're right. I meant to this for V3 but I guess I forgot. Will fix.
-Andrew
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