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Message-ID: <1430506447-29074-12-git-send-email-rklein@nvidia.com>
Date: Fri, 1 May 2015 14:53:58 -0400
From: Rhyland Klein <rklein@...dia.com>
To: Peter De Schrijver <pdeschrijver@...dia.com>
CC: Mike Turquette <mturquette@...aro.org>,
Stephen Warren <swarren@...dotorg.org>,
Stephen Boyd <sboyd@...eaurora.org>,
Thierry Reding <thierry.reding@...il.com>,
Alexandre Courbot <gnurou@...il.com>,
linux-clk@...r.kernel.org, linux-tegra@...r.kernel.org,
linux-kernel@...r.kernel.org, Rhyland Klein <rklein@...dia.com>,
Bill Huang <bilhuang@...dia.com>
Subject: [PATCH v3 11/20] clk: tegra: pll: Add code to handle if resets are supported by PLL
From: Bill Huang <bilhuang@...dia.com>
If a PLL has a reset_reg specified, properly handle that in the
enable/disable logic paths.
Signed-off-by: Bill Huang <bilhuang@...dia.com>
---
v2:
- Moved reset logic to _clk_pll_enable/disable as well
drivers/clk/tegra/clk-pll.c | 12 ++++++++++++
drivers/clk/tegra/clk.h | 2 ++
2 files changed, 14 insertions(+)
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index 0b9cbe12a3eb..3c40a8136136 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -311,6 +311,12 @@ static void _clk_pll_enable(struct clk_hw *hw)
udelay(2);
}
+ if (pll->params->reset_reg) {
+ val = pll_readl(pll->params->reset_reg, pll);
+ val &= ~BIT(pll->params->reset_bit_idx);
+ pll_writel(val, pll->params->reset_reg, pll);
+ }
+
clk_pll_enable_lock(pll);
val = pll_readl_base(pll);
@@ -343,6 +349,12 @@ static void _clk_pll_disable(struct clk_hw *hw)
writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);
}
+ if (pll->params->reset_reg) {
+ val = pll_readl(pll->params->reset_reg, pll);
+ val |= BIT(pll->params->reset_bit_idx);
+ pll_writel(val, pll->params->reset_reg, pll);
+ }
+
if (pll->params->iddq_reg) {
val = pll_readl(pll->params->iddq_reg, pll);
val |= BIT(pll->params->iddq_bit_idx);
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index b009c803f277..142999f1cd24 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -217,6 +217,8 @@ struct tegra_clk_pll_params {
u32 lock_enable_bit_idx;
u32 iddq_reg;
u32 iddq_bit_idx;
+ u32 reset_reg;
+ u32 reset_bit_idx;
u32 sdm_din_reg;
u32 sdm_din_mask;
u32 sdm_ctrl_reg;
--
1.7.9.5
--
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