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Message-ID: <CANLzEksajPjf1VH8Zn-1oXhgL8f-b7GuCBprExTP-w18WbCC4A@mail.gmail.com>
Date: Mon, 4 May 2015 13:35:09 -0700
From: Benson Leung <bleung@...omium.org>
To: Rhyland Klein <rklein@...dia.com>
Cc: Peter De Schrijver <pdeschrijver@...dia.com>,
Mike Turquette <mturquette@...aro.org>,
Stephen Warren <swarren@...dotorg.org>,
Stephen Boyd <sboyd@...eaurora.org>,
Thierry Reding <thierry.reding@...il.com>,
Alexandre Courbot <gnurou@...il.com>,
linux-clk@...r.kernel.org, linux-tegra@...r.kernel.org,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
Bill Huang <bilhuang@...dia.com>
Subject: Re: [PATCH v4 06/20] clk: tegra: pll-params: change misc_reg count
from 3 -> 6
On Mon, May 4, 2015 at 9:37 AM, Rhyland Klein <rklein@...dia.com> wrote:
> From: Bill Huang <bilhuang@...dia.com>
>
> New SoC's may have more then 3 MISC registers, so bump up the
> array size and use a #define to be more informative about the value.
>
> Signed-off-by: Bill Huang <bilhuang@...dia.com>
> ---
> drivers/clk/tegra/clk.h | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
> index 5759b8bfb80e..8e7361886cf9 100644
> --- a/drivers/clk/tegra/clk.h
> +++ b/drivers/clk/tegra/clk.h
> @@ -156,6 +156,8 @@ struct div_nmp {
> u8 override_divp_shift;
> };
>
> +#define MAX_PLL_MISC_REG_COUNT 6
> +
> /**
> * struct clk_pll_params - PLL parameters
> *
> @@ -213,7 +215,7 @@ struct tegra_clk_pll_params {
> u32 iddq_bit_idx;
> u32 aux_reg;
> u32 dyn_ramp_reg;
> - u32 ext_misc_reg[3];
> + u32 ext_misc_reg[MAX_PLL_MISC_REG_COUNT];
> u32 pmc_divnm_reg;
> u32 pmc_divp_reg;
> u32 flags;
Missing kernel doc above for ext_misc_reg and some other surrounding members.
Otherwise,
Reviewed-by: Benson Leung <bleung@...omium.org>
--
Benson Leung
Software Engineer, Chrom* OS
bleung@...omium.org
--
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