linux-kernel - Re: [PATCH v4 10/20] clk: tegra: pll: Add logic for out-of-table rates for T210

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Date:	Mon, 4 May 2015 16:34:03 -0700
From:	Benson Leung <bleung@...omium.org>
To:	Rhyland Klein <rklein@...dia.com>
Cc:	Peter De Schrijver <pdeschrijver@...dia.com>,
	Mike Turquette <mturquette@...aro.org>,
	Stephen Warren <swarren@...dotorg.org>,
	Stephen Boyd <sboyd@...eaurora.org>,
	Thierry Reding <thierry.reding@...il.com>,
	Alexandre Courbot <gnurou@...il.com>,
	linux-clk@...r.kernel.org, linux-tegra@...r.kernel.org,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v4 10/20] clk: tegra: pll: Add logic for out-of-table
 rates for T210

On Mon, May 4, 2015 at 9:37 AM, Rhyland Klein <rklein@...dia.com> wrote:
> For Tegra210, the logic to calculate out-of-table rates is different
> from previous generations. Add callbacks that can be overridden to
> allow for different ways of calculating rates. Default to
> _cal_rate when not specified.

You should mention that you're adding a new flag and new members that
may override mdiv as well.

>
> Based on original work by Aleksandr Frid <afrid@...dia.com>
>
> Signed-off-by: Rhyland Klein <rklein@...dia.com>
> ---
> diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
> index 3f92f1ad3961..b63ef31a2d7a 100644
> --- a/drivers/clk/tegra/clk.h
> +++ b/drivers/clk/tegra/clk.h
> @@ -199,6 +199,8 @@ struct div_nmp {
>   *     base register.
>   * TEGRA_PLL_BYPASS - PLL has bypass bit
>   * TEGRA_PLL_HAS_LOCK_ENABLE - PLL has bit to enable lock monitoring
> + * TEGRA_MDIV_NEW - Switch to new method for calculating fixed mdiv
> + *     it may be more accurate (especially if SDM present)
>   */
>  struct tegra_clk_pll_params {
>         unsigned long   input_min;
> @@ -235,7 +237,13 @@ struct tegra_clk_pll_params {
>         struct div_nmp  *div_nmp;
>         struct tegra_clk_pll_freq_table *freq_table;
>         unsigned long   fixed_rate;
> +       bool            vco_out;

vco_out is unused and unrelated to this change?

> +       u16             mdiv_default;
> +       u32     (*round_p_to_pdiv)(u32 p, u32 *pdiv);
>         void    (*set_gain)(struct tegra_clk_pll_freq_table *cfg);
> +       int     (*calc_rate)(struct clk_hw *hw,
> +                       struct tegra_clk_pll_freq_table *cfg,
> +                       unsigned long rate, unsigned long parent_rate);

Add kerneldoc for new members.


-- 
Benson Leung
Software Engineer, Chrom* OS
bleung@...omium.org
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