Message-ID: <20150507144128.GA26094@ulmo.nvidia.com>
Date:	Thu, 7 May 2015 16:41:30 +0200
From:	Thierry Reding <treding@...dia.com>
To:	Rob Clark <robdclark@...il.com>
CC:	One Thousand Gnomes <gnomes@...rguk.ukuu.org.uk>,
	Benjamin Gaignard <benjamin.gaignard@...aro.org>,
	"linux-media@...r.kernel.org" <linux-media@...r.kernel.org>,
	Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
	"dri-devel@...ts.freedesktop.org" <dri-devel@...ts.freedesktop.org>,
	Hans Verkuil <hverkuil@...all.nl>,
	"Laurent Pinchart" <laurent.pinchart@...asonboard.com>,
	Dave Airlie <airlied@...hat.com>,
	Sumit Semwal <sumit.semwal@...aro.org>,
	Tom Gall <tom.gall@...aro.org>,
	Daniel Vetter <daniel.vetter@...ll.ch>
Subject: Re: [RFC] How implement Secure Data Path ?

On Wed, May 06, 2015 at 07:29:56AM -0400, Rob Clark wrote:
> On Wed, May 6, 2015 at 4:35 AM, Daniel Vetter <daniel@...ll.ch> wrote:
> > On Tue, May 05, 2015 at 05:54:05PM +0100, One Thousand Gnomes wrote:
> >> > First what is Secure Data Path ? SDP is a set of hardware features to garanty
> >> > that some memories regions could only be read and/or write by specific hardware
> >> > IPs. You can imagine it as a kind of memory firewall which grant/revoke
> >> > accesses to memory per devices. Firewall configuration must be done in a trusted
> >> > environment: for ARM architecture we plan to use OP-TEE + a trusted
> >> > application to do that.
> >>
> >> It's not just an ARM feature so any basis for this in the core code
> >> should be generic, whether its being enforced by ARM SDP, various Intel
> >> feature sets or even via a hypervisor.
> >>
> >> > I have try 2 "hacky" approachs with dma_buf:
> >> > - add a secure field in dma_buf structure and configure firewall in
> >> >   dma_buf_{map/unmap}_attachment() functions.
> >>
> >> How is SDP not just another IOMMU. The only oddity here is that it
> >> happens to configure buffers the CPU can't touch and it has a control
> >> mechanism that is designed to cover big media corp type uses where the
> >> threat model is that the system owner is the enemy. Why does anything care
> >> about it being SDP, there are also generic cases this might be a useful
> >> optimisation (eg knowing the buffer isn't CPU touched so you can optimise
> >> cache flushing).
> >>
> >> The control mechanism is a device/platform detail as with any IOMMU. It
> >> doesn't matter who configures it or how, providing it happens.
> >>
> >> We do presumably need some small core DMA changes - anyone trying to map
> >> such a buffer into CPU space needs to get a warning or error but what
> >> else ?
> >>
> >> > >From buffer allocation point of view I also facing a problem because when v4l2
> >> > or drm/kms are exporting buffers by using dma_buf they don't attaching
> >> > themself on it and never call dma_buf_{map/unmap}_attachment(). This is not
> >> > an issue in those framework while it is how dma_buf exporters are
> >> > supposed to work.
> >>
> >> Which could be addressed if need be.
> >>
> >> So if "SDP" is just another IOMMU feature, just as stuff like IMR is on
> >> some x86 devices, and hypervisor enforced protection is on assorted
> >> platforms why do we need a special way to do it ? Is there anything
> >> actually needed beyond being able to tell the existing DMA code that this
> >> buffer won't be CPU touched and wiring it into the DMA operations for the
> >> platform ?
> >
> > Iirc most of the dma api stuff gets unhappy when memory isn't struct page
> > backed. In i915 we do use sg tables everywhere though (even for memory not
> > backed by struct page, e.g. the "stolen" range the bios prereserves), but
> > we fill those out manually.
> >
> > A possible generic design I see is to have a secure memory allocator
> > device which doesn nothing else but hand out dma-bufs. With that we can
> > hide the platform-specific allocation methods in there (some need to
> > allocate from carveouts, other just need to mark the pages specifically).
> > Also dma-buf has explicit methods for cpu access, which are allowed to
> > fail. And using the dma-buf attach tracking we can also reject dma to
> > devices which cannot access the secure memory. Given all that I think
> > going through the dma-buf interface but with a special-purpose allocator
> > seems to fit.
> >
> > I'm not sure whether a special iommu is a good idea otoh: I'd expect that
> > for most devices the driver would need to decide about which iommu to pick
> > (or maybe keep track of some special flags for an extended dma_map
> > interface). At least looking at gpu drivers using iommus would require
> > special code, whereas fully hiding all this behind the dma-buf interface
> > should fit in much better.
> 
> 
> jfwiw, I'd fully expect devices to be dealing with a mix of secure and
> insecure buffers, so I'm also not really sure how the 'special iommu'
> plan would play out..
> 
> I think 'secure' allocator device sounds attractive from PoV of
> separating out platform nonsense.. not sure if it is exactly that
> easy, since importing device probably needs to set some special bits
> here and there..

I would expect there to be a central entity handing out the secure
buffers and that the entity would have the ability to grant access to
the buffers to devices. So I'm thinking that the exporter would deal
with this in the ->attach() operation. That's passed a struct device,
so we should be able to retrieve the information necessary somehow.

Then again, maybe things will be more involved than that. I think the
way this typically works in consumer devices is that you need to jump
into secure firmware to get access granted. For example on Tegra most
registers that control this are TrustZone-protected, so if you don't
happen to be lucky enough to be running the kernel in secure mode you
can't enable access to secure memory from the kernel.

As Alan mentioned before this is designed with the assumption that the
user is not to be trusted, so the OEM must make sure that the chain of
trust is upheld. In practice that means that consumer devices will run
some secure firmware that can't be replaced and which boots the kernel
in non-secure mode, thereby disallowing the kernel from touching these
registers that could potentially expose protected content to untrusted
consumers.

In practice I think the result is that secure firmware sets up secure
memory (VPR on Tegra) and then lets the kernel know its geometry. The
kernel is then free to manage the VPR as it sees fit. If the devices
need to deal with both secure and non-secure memory, I'm not exactly
sure how the above security model is supposed to hold. If the kernel
is free to program any address into the device, then it would be easy
to trick it into writing to some region that the CPU can access. I'm
fairly sure that there's some mechanism to disallow that, but I don't
know exactly how it's implemented.

Thierry

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