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Message-ID: <20150508111918.GE27504@twins.programming.kicks-ass.net>
Date: Fri, 8 May 2015 13:19:18 +0200
From: Peter Zijlstra <peterz@...radead.org>
To: Andi Kleen <andi@...stfloor.org>
Cc: kan.liang@...el.com, eranian@...gle.com, acme@...radead.org,
linux-kernel@...r.kernel.org, Andi Kleen <ak@...ux.intel.com>
Subject: Re: [PATCH 8/9] perf, x86: Optimize v4 LBR unfreezing
On Thu, May 07, 2015 at 03:56:31PM -0700, Andi Kleen wrote:
> From: Andi Kleen <ak@...ux.intel.com>
>
> In Arch perfmon v4 the GLOBAL_STATUS reset automatically unfreezes
> LBRs. So no need to do it manually in the LBR code. Add a check
> to skip it.
>
> Signed-off-by: Andi Kleen <ak@...ux.intel.com>
> ---
> arch/x86/kernel/cpu/perf_event_intel_lbr.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/arch/x86/kernel/cpu/perf_event_intel_lbr.c b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
> index 6c48c97..64d3122 100644
> --- a/arch/x86/kernel/cpu/perf_event_intel_lbr.c
> +++ b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
> @@ -147,6 +147,13 @@ static void __intel_pmu_lbr_enable(bool pmi)
> wrmsrl(MSR_LBR_SELECT, lbr_select);
> }
>
> + /*
> + * No need to unfreeze manually, as v4 can do that as part
> + * of the GLOBAL_STATUS ack.
> + */
> + if (pmi && x86_pmu.version >= 4)
> + return;
> +
But that block above is !pmi, so strictly exclusive with this condition.
So why not put this at the start?
> rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
> orig_debugctl = debugctl;
> debugctl |= DEBUGCTLMSR_LBR;
--
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