linux-kernel - Re: [PATCH v3 2/7] mmc: mediatek: Add Mediatek MMC driver

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Message-ID: <CAPDyKFr5N_08HbLuY=4Wfv1BoVQLVR-VW+NKh_umL1hzi_KozA@mail.gmail.com>
Date:	Fri, 8 May 2015 14:12:59 +0200
From:	Ulf Hansson <ulf.hansson@...aro.org>
To:	Chaotian Jing <chaotian.jing@...iatek.com>
Cc:	Rob Herring <robh+dt@...nel.org>,
	Matthias Brugger <matthias.bgg@...il.com>,
	Chris Ball <chris@...ntf.net>,
	Mark Rutland <mark.rutland@....com>,
	James Liao <jamesjj.liao@...iatek.com>,
	srv_heupstream <srv_heupstream@...iatek.com>,
	Arnd Bergmann <arnd@...db.de>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	Hongzhou Yang <hongzhou.yang@...iatek.com>,
	Catalin Marinas <catalin.marinas@....com>,
	linux-mmc <linux-mmc@...r.kernel.org>,
	Will Deacon <will.deacon@....com>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"linux-gpio@...r.kernel.org" <linux-gpio@...r.kernel.org>,
	Sascha Hauer <kernel@...gutronix.de>,
	"Joe.C" <yingjoe.chen@...iatek.com>,
	Eddie Huang <eddie.huang@...iatek.com>,
	Bin Zhang (章斌) <bin.zhang@...iatek.com>,
	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>,
	linux-mediatek@...ts.infradead.org
Subject: Re: [PATCH v3 2/7] mmc: mediatek: Add Mediatek MMC driver

On 7 May 2015 at 03:42, Chaotian Jing <chaotian.jing@...iatek.com> wrote:
> Dear Ulf,
>
> Thanks!
> Below is my comment:
>
> On Wed, 2015-05-06 at 18:31 +0200, Ulf Hansson wrote:
>> On 6 May 2015 at 08:54, chaotian.jing <chaotian.jing@...iatek.com> wrote:
>> > Dear Ulf,
>> >
>> > Thanks for your review.
>> > I must do a explain of our MMC host:
>> > Source clock is source clock of the MMC bus, MMC host has a divider to
>> > get different bus clock frequency. now the runtime suspend is gating
>> > this clock.
>> >
>> > Hclk is the power domain of the MMC host, if Hclk is gated, the MMC host
>> > cannot work(all registers readout is zero). and, all registers would be
>> > reset to default value if Hclk is gated/ungated.
>> > At MT8173, MSDC0 and MSDC2 has independent Hclk, MSDC1 and MSDC3's Hclk
>> > was controlled by "Infra module".
> Sorry for mistake, MSDC0 and MSDC3 has independent Hclk, MSDC1 and
> MSDC2's Hclk was controlled by "Infra module". the Infra module is a
> "power saving module", when the system go to sleep, Infra module will be
> set and MSDC1 & MSDC2's Hclk will be gated automatically.
>>
>> Thanks for clarifying!
>>
>> I don't have enough knowledge about your SoC to understand the detail,
>> but it seems like we are mixing clocks and power domains. I would
>> rather keep this separate - if the HW allows it.
>>
>> I guess the key question I have is the following:
>> 1) Is it hardware wise possible to gate the hclk, but without gating
>> the power domain?
>> 2) At what level is the reference counting done for each device in the
>> power domain? In HW or in sofftware?
>>
>
> Actually, Our MMC host do not have power domain, all the control of the
> host is the Hclk.

Okay, but I am not sure that fully answered my question.

You said that hclk will be gated when the power domain gets gated. And
the power domain (infra module, right?) will be gated at system PM
sleep. And when that happens the mmc controller loses register
context.

But, again, can hclk be gated without gating the power domain?

No matter what, it seems like a good idea to gate the power domain
when all clients of it are idle. Yes we would need to manage register
save/restore context, but on the other hand allow you to save more
power, right?

Kind regards
Uffe
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