linux-kernel - Re: [PATCH 2/4] soc: Mediatek: Add SCPSYS power domain driver

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Date:	Fri, 8 May 2015 14:51:02 +0200
From:	Sascha Hauer <s.hauer@...gutronix.de>
To:	Matthias Brugger <matthias.bgg@...il.com>
Cc:	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	linux-mediatek@...ts.infradead.org,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	=Sascha Hauer <kernel@...gutronix.de>,
	Kevin Hilman <khilman@...nel.org>
Subject: Re: [PATCH 2/4] soc: Mediatek: Add SCPSYS power domain driver

On Fri, May 08, 2015 at 02:28:37PM +0200, Matthias Brugger wrote:
> 2015-05-08 14:19 GMT+02:00 Sascha Hauer <s.hauer@...gutronix.de>:
> > On Fri, May 08, 2015 at 02:16:06PM +0200, Matthias Brugger wrote:
> >> 2015-03-10 16:41 GMT+01:00 Sascha Hauer <s.hauer@...gutronix.de>:
> >> > +static int scpsys_power_on(struct generic_pm_domain *genpd)
> >> > +{
> >> > +       struct scp_domain *scpd = container_of(genpd, struct scp_domain, pmd);
> >> > +       struct scp *scp = scpd->scp;
> >> > +       struct scp_domain_data *data = scpd->data;
> >> > +       unsigned long expired;
> >> > +       void __iomem *ctl_addr = scpd->scp->base + data->ctl_offs;
> >> > +       u32 sram_pdn_ack = data->sram_pdn_ack_bits;
> >> > +       u32 val;
> >> > +       int ret;
> >> > +
> >> > +       val = readl(ctl_addr);
> >> > +       val |= PWR_ON_BIT;
> >> > +       writel(val, ctl_addr);
> >> > +       val |= PWR_ON_2ND_BIT;
> >> > +       writel(val, ctl_addr);
> >> > +
> >> > +       /* wait until PWR_ACK = 1 */
> >> > +       expired = jiffies + HZ;
> >> > +       while (!(readl(scp->base + SPM_PWR_STATUS) & data->sta_mask) ||
> >> > +                       !(readl(scp->base + SPM_PWR_STATUS_2ND) & data->sta_mask)) {
> >> > +               cpu_relax();
> >> > +               if (time_after(jiffies, expired)) {
> >> > +                       ret = -EIO;
> >> > +                       goto out;
> >> > +               }
> >> > +       }
> >> > +
> >> > +       val &= ~PWR_CLK_DIS_BIT;
> >> > +       writel(val, ctl_addr);
> >> > +
> >> > +       val &= ~PWR_ISO_BIT;
> >> > +       writel(val, ctl_addr);
> >> > +
> >> > +       val |= PWR_RST_B_BIT;
> >> > +       writel(val, ctl_addr);
> >> > +
> >> > +       val &= ~data->sram_pdn_bits;
> >> > +       writel(val, ctl_addr);
> >> > +
> >> > +       /* wait until SRAM_PDN_ACK all 0 */
> >> > +       expired = jiffies + HZ;
> >> > +       while (sram_pdn_ack && (readl(ctl_addr) & sram_pdn_ack)) {
> >>
> >> I think "sram_pdn_ack &&" was added accidently here. It is always
> >> bigger then zero.
> >
> > Nope, it's zero for MT8173_POWER_DOMAIN_MFG_ASYNC.
> 
> In probe you turn on all power domains defined in scp_domain_data[].
> So all but MT8173_POWER_DOMAIN_MFG_ASYNC will fail.
> Does this make sense?

What makes you think that enabling the domains will fail? That doesn't
happen.

Sascha

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