linux-kernel - [PATCH 4.0 12/72] MIPS: Octeon: Remove udelay() causing huge IRQ latency

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Date:	Mon, 11 May 2015 10:54:18 -0700
From:	Greg Kroah-Hartman <gregkh@...uxfoundation.org>
To:	linux-kernel@...r.kernel.org, stable@...r.kernel.org
Cc:	Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
	Alexander Sverdlin <alexander.sverdlin@...ia.com>,
	linux-mips@...ux-mips.org, David Daney <ddaney@...ium.com>,
	Rob Herring <robh@...nel.org>, Jiri Kosina <jkosina@...e.cz>,
	Randy Dunlap <rdunlap@...radead.org>,
	Masanari Iida <standby24x7@...il.com>,
	Bjorn Helgaas <bhelgaas@...gle.com>,
	Mathias <mathias.rulf@...ia.com>,
	Ralf Baechle <ralf@...ux-mips.org>
Subject: [PATCH 4.0 12/72] MIPS: Octeon: Remove udelay() causing huge IRQ latency

4.0-stable review patch.  If anyone has any objections, please let me know.

------------------


From: Alexander Sverdlin <alexander.sverdlin@...ia.com>

Commit 73bf3c2a500b2db8ac966469591196bf55afb409 upstream.

udelay() in PCI/PCIe read/write callbacks cause 30ms IRQ latency on Octeon
platforms because these operations are called from PCI_OP_READ() and
PCI_OP_WRITE() under raw_spin_lock_irqsave().

Signed-off-by: Alexander Sverdlin <alexander.sverdlin@...ia.com>
Cc: linux-mips@...ux-mips.org
Cc: David Daney <ddaney@...ium.com>
Cc: Rob Herring <robh@...nel.org>
Cc: Jiri Kosina <jkosina@...e.cz>
Cc: Randy Dunlap <rdunlap@...radead.org>
Cc: Masanari Iida <standby24x7@...il.com>
Cc: Bjorn Helgaas <bhelgaas@...gle.com>
Cc: Mathias <mathias.rulf@...ia.com>
Patchwork: https://patchwork.linux-mips.org/patch/9576/
Signed-off-by: Ralf Baechle <ralf@...ux-mips.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@...uxfoundation.org>
---
 arch/mips/include/asm/octeon/pci-octeon.h |    3 ---
 arch/mips/pci/pci-octeon.c                |    6 ------
 arch/mips/pci/pcie-octeon.c               |    8 --------
 3 files changed, 17 deletions(-)

--- a/arch/mips/include/asm/octeon/pci-octeon.h
+++ b/arch/mips/include/asm/octeon/pci-octeon.h
@@ -11,9 +11,6 @@
 
 #include <linux/pci.h>
 
-/* Some PCI cards require delays when accessing config space. */
-#define PCI_CONFIG_SPACE_DELAY 10000
-
 /*
  * The physical memory base mapped by BAR1.  256MB at the end of the
  * first 4GB.
--- a/arch/mips/pci/pci-octeon.c
+++ b/arch/mips/pci/pci-octeon.c
@@ -271,9 +271,6 @@ static int octeon_read_config(struct pci
 	pci_addr.s.func = devfn & 0x7;
 	pci_addr.s.reg = reg;
 
-#if PCI_CONFIG_SPACE_DELAY
-	udelay(PCI_CONFIG_SPACE_DELAY);
-#endif
 	switch (size) {
 	case 4:
 		*val = le32_to_cpu(cvmx_read64_uint32(pci_addr.u64));
@@ -308,9 +305,6 @@ static int octeon_write_config(struct pc
 	pci_addr.s.func = devfn & 0x7;
 	pci_addr.s.reg = reg;
 
-#if PCI_CONFIG_SPACE_DELAY
-	udelay(PCI_CONFIG_SPACE_DELAY);
-#endif
 	switch (size) {
 	case 4:
 		cvmx_write64_uint32(pci_addr.u64, cpu_to_le32(val));
--- a/arch/mips/pci/pcie-octeon.c
+++ b/arch/mips/pci/pcie-octeon.c
@@ -1762,14 +1762,6 @@ static int octeon_pcie_write_config(unsi
 	default:
 		return PCIBIOS_FUNC_NOT_SUPPORTED;
 	}
-#if PCI_CONFIG_SPACE_DELAY
-	/*
-	 * Delay on writes so that devices have time to come up. Some
-	 * bridges need this to allow time for the secondary busses to
-	 * work
-	 */
-	udelay(PCI_CONFIG_SPACE_DELAY);
-#endif
 	return PCIBIOS_SUCCESSFUL;
 }
 


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