linux-kernel - Re: [PATCH v5 15/21] clk: tegra: pll: Add dyn

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Message-ID: <CANLzEks_bEnpyKuVHJEn8XZbdMDaqj9bQ+SjpgrM-uQo0W28Ug@mail.gmail.com>
Date:	Wed, 13 May 2015 15:20:31 -0700
From:	Benson Leung <bleung@...omium.org>
To:	Rhyland Klein <rklein@...dia.com>
Cc:	Peter De Schrijver <pdeschrijver@...dia.com>,
	Mike Turquette <mturquette@...aro.org>,
	Stephen Warren <swarren@...dotorg.org>,
	Stephen Boyd <sboyd@...eaurora.org>,
	Thierry Reding <thierry.reding@...il.com>,
	Alexandre Courbot <gnurou@...il.com>,
	Bill Huang <bilhuang@...dia.com>,
	Paul Walmsley <pwalmsley@...dia.com>,
	Jim Lin <jilin@...dia.com>, linux-clk@...r.kernel.org,
	linux-tegra@...r.kernel.org,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v5 15/21] clk: tegra: pll: Add dyn_ramp callback

On Tue, May 12, 2015 at 10:23 AM, Rhyland Klein <rklein@...dia.com> wrote:
> From: Bill Huang <bilhuang@...dia.com>
>
> Add a callback to the pll_params for custom dynamic ramping
> functions which can be specified per PLL.
>
> Signed-off-by: Bill Huang <bilhuang@...dia.com>

Modulo kerneldoc addition,
Reviewed-by: Benson Leung <bleung@...omium.org>

> ---
>  drivers/clk/tegra/clk.h |    4 ++++
>  1 file changed, 4 insertions(+)
>
> diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
> index 330729a822cf..a61d388364b3 100644
> --- a/drivers/clk/tegra/clk.h
> +++ b/drivers/clk/tegra/clk.h
> @@ -160,6 +160,8 @@ struct div_nmp {
>
>  #define MAX_PLL_MISC_REG_COUNT 6
>
> +struct tegra_clk_pll;
> +
>  /**
>   * struct tegra_clk_pll_params - PLL parameters
>   *
> @@ -271,6 +273,8 @@ struct tegra_clk_pll_params {
>                         unsigned long rate, unsigned long parent_rate);
>         unsigned long   (*adjust_vco)(struct tegra_clk_pll_params *pll_params,
>                                 unsigned long parent_rate);
> +       int     (*dyn_ramp)(struct tegra_clk_pll *pll,
> +                       struct tegra_clk_pll_freq_table *cfg);

Please add kerneldoc for dyn_ramp member above.

>  };
>
>  #define TEGRA_PLL_USE_LOCK BIT(0)
> --
> 1.7.9.5
>
> --
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-- 
Benson Leung
Software Engineer, Chrom* OS
bleung@...omium.org
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