linux-kernel - RE: [PATCH 8/8] ARM: mvebu: a38x: Enable A38x XOR engine features

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Message-ID: <14c9a6d3ba4c46f89880e4c1b4494dbb@IL-EXCH02.marvell.com>
Date:	Wed, 13 May 2015 07:16:34 +0000
From:	Lior Amsalem <alior@...vell.com>
To:	Andrew Lunn <andrew@...n.ch>,
	Maxime Ripard <maxime.ripard@...e-electrons.com>
CC:	Vinod Koul <vinod.koul@...el.com>,
	Dan Williams <dan.j.williams@...el.com>,
	Gregory Clement <gregory.clement@...e-electrons.com>,
	Jason Cooper <jason@...edaemon.net>,
	Sebastian Hesselbarth <sebastian.hesselbarth@...il.com>,
	"dmaengine@...r.kernel.org" <dmaengine@...r.kernel.org>,
	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"linux-crypto@...r.kernel.org" <linux-crypto@...r.kernel.org>,
	Thomas Petazzoni <thomas@...e-electrons.com>,
	Herbert Xu <herbert@...dor.apana.org.au>,
	"David S. Miller" <davem@...emloft.net>
Subject: RE: [PATCH 8/8] ARM: mvebu: a38x: Enable A38x XOR engine features

> From: Andrew Lunn [mailto:andrew@...n.ch]
> Sent: Tuesday, May 12, 2015 7:13 PM
> 
> On Tue, May 12, 2015 at 05:37:43PM +0200, Maxime Ripard wrote:
> > From: Lior Amsalem <alior@...vell.com>
> >
> > The new XOR engine has a new compatible of its own, together with new
> > channel capabilities.
> >
> > Use that new compatible now that we have a driver that can handle it.
> >
> > Signed-off-by: Lior Amsalem <alior@...vell.com>
> > Reviewed-by: Ofer Heifetz <oferh@...vell.com>
> > Reviewed-by: Nadav Haklai <nadavh@...vell.com>
> > Tested-by: Nadav Haklai <nadavh@...vell.com>
> > ---
> >  arch/arm/boot/dts/armada-38x.dtsi | 20 ++++++--------------
> >  1 file changed, 6 insertions(+), 14 deletions(-)
> >
> > diff --git a/arch/arm/boot/dts/armada-38x.dtsi
> > b/arch/arm/boot/dts/armada-38x.dtsi
> > index ed2dd8ba4080..6d07b7389415 100644
> > --- a/arch/arm/boot/dts/armada-38x.dtsi
> > +++ b/arch/arm/boot/dts/armada-38x.dtsi
> > @@ -448,7 +448,7 @@
> >  			};
> >
> >  			xor@...00 {
> > -				compatible = "marvell,orion-xor";
> > +				compatible = "marvell,a38x-xor";
> >  				reg = <0x60800 0x100
> >  				       0x60a00 0x100>;
> >  				clocks = <&gateclk 22>;
> > @@ -458,17 +458,13 @@
> >  					interrupts = <GIC_SPI 22
> IRQ_TYPE_LEVEL_HIGH>;
> >  					dmacap,memcpy;
> >  					dmacap,xor;
> > -				};
> > -				xor01 {
> > -					interrupts = <GIC_SPI 23
> IRQ_TYPE_LEVEL_HIGH>;
> > -					dmacap,memcpy;
> > -					dmacap,xor;
> > -					dmacap,memset;
> > +					dmacap,pq;
> > +					dmacap,interrupt;
> 
> Does this mean the hardware only has one channel?
> And memset is no longer supported?
> 

The hardware has two channels per engine and two engines.
However, both on HW side (both channels are on the same "bus port")
and SW (the dma subsystem will assign one channel per CPU).
we found it's better (performance wise) to use only one channel on each engine
and let the framework assign one per CPU.
This way, descriptors chaining was better (cause of the depended descriptors
problem) and overall interrupt number reduced.

Yes, since memset is a problematic one. It can only be done via registers
(and not on descriptors level) plus no one really needs it...

>     Andrew
> 
> 
> >  				};
> >  			};
> >
> >  			xor@...00 {
> > -				compatible = "marvell,orion-xor";
> > +				compatible = "marvell,a38x-xor";
> >  				reg = <0x60900 0x100
> >  				       0x60b00 0x100>;
> >  				clocks = <&gateclk 28>;
> > @@ -478,12 +474,8 @@
> >  					interrupts = <GIC_SPI 65
> IRQ_TYPE_LEVEL_HIGH>;
> >  					dmacap,memcpy;
> >  					dmacap,xor;
> > -				};
> > -				xor11 {
> > -					interrupts = <GIC_SPI 66
> IRQ_TYPE_LEVEL_HIGH>;
> > -					dmacap,memcpy;
> > -					dmacap,xor;
> > -					dmacap,memset;
> > +					dmacap,pq;
> > +					dmacap,interrupt;
> >  				};
> >  			};
> >
> > --
> > 2.4.0
> >


Regards,
Lior Amsalem

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