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Message-Id: <a8ecee7fe315aa06a3b0a95f613aa58400e9c092.1431761807.git.jslaby@suse.cz>
Date:	Sat, 16 May 2015 09:36:18 +0200
From:	Jiri Slaby <jslaby@...e.cz>
To:	stable@...r.kernel.org
Cc:	linux-kernel@...r.kernel.org, Huacai Chen <chenhc@...ote.com>,
	"Steven J. Hill" <Steven.Hill@...tec.com>,
	linux-mips@...ux-mips.org, Fuxin Zhang <zhangfx@...ote.com>,
	Zhangjin Wu <wuzhangjin@...il.com>,
	Ralf Baechle <ralf@...ux-mips.org>, Jiri Slaby <jslaby@...e.cz>
Subject: [PATCH 3.12 018/142] MIPS: Hibernate: flush TLB entries earlier

From: Huacai Chen <chenhc@...ote.com>

3.12-stable review patch.  If anyone has any objections, please let me know.

===============

commit a843d00d038b11267279e3b5388222320f9ddc1d upstream.

We found that TLB mismatch not only happens after kernel resume, but
also happens during snapshot restore. So move it to the beginning of
swsusp_arch_suspend().

Signed-off-by: Huacai Chen <chenhc@...ote.com>
Cc: Steven J. Hill <Steven.Hill@...tec.com>
Cc: linux-mips@...ux-mips.org
Cc: Fuxin Zhang <zhangfx@...ote.com>
Cc: Zhangjin Wu <wuzhangjin@...il.com>
Patchwork: https://patchwork.linux-mips.org/patch/9621/
Signed-off-by: Ralf Baechle <ralf@...ux-mips.org>
Signed-off-by: Jiri Slaby <jslaby@...e.cz>
---
 arch/mips/power/hibernate.S | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/mips/power/hibernate.S b/arch/mips/power/hibernate.S
index 32a7c828f073..e7567c8a9e79 100644
--- a/arch/mips/power/hibernate.S
+++ b/arch/mips/power/hibernate.S
@@ -30,6 +30,8 @@ LEAF(swsusp_arch_suspend)
 END(swsusp_arch_suspend)
 
 LEAF(swsusp_arch_resume)
+	/* Avoid TLB mismatch during and after kernel resume */
+	jal local_flush_tlb_all
 	PTR_L t0, restore_pblist
 0:
 	PTR_L t1, PBE_ADDRESS(t0)   /* source */
@@ -43,7 +45,6 @@ LEAF(swsusp_arch_resume)
 	bne t1, t3, 1b
 	PTR_L t0, PBE_NEXT(t0)
 	bnez t0, 0b
-	jal local_flush_tlb_all /* Avoid TLB mismatch after kernel resume */
 	PTR_LA t0, saved_regs
 	PTR_L ra, PT_R31(t0)
 	PTR_L sp, PT_R29(t0)
-- 
2.3.7

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