ads7845(page 8):

Figure 5 shows the typical operation of the ADS7845’s digital
interface. This diagram assumes that the source of the digital signals
is a microcontroller or digital signal processor with a basic serial
interface. Each communication between the processor and the converter
consists of 8 clock cycles. 

One complete conversion can be accomplished
with three serial communications, for a total of 24 clock cycles on the
DCLK input.  

The first 8 clock cycles are used to provide the control byte
via the DIN pin. When the converter has enough information about
the following conversion to set the input multiplexer, switches, and
reference inputs appropriately, 

the converter enters the acquisition (sample) mode and, 
if needed, the internal switches are turned on. After three more 
clock cycles, the control byte is complete and the converter
enters the conversion mode. 
At this point, the input sample/hold goes into the 
hold mode and the internal switches may turn off. 
The next 12 clock cycles accomplish the actual analog-to-digital conversion. If the
conversion is ratiometric (SER/DFR LOW), the internal switches are on
during the conversion. A 13th clock cycle is needed for the last bit of
the conversion result. Three more clock cycles are needed to complete
the last byte (DOUT will be LOW). These will be ignored by the converter.