linux-kernel - [RFC] arm: Add for atomic half word exchange

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Message-id: <1795987946.405311432034410830.JavaMail.weblogic@ep2mlwas07a>
Date:	Tue, 19 May 2015 11:20:15 +0000 (GMT)
From:	Sarbojit Ganguly <ganguly.s@...sung.com>
To:	Arnd Bergmann <arnd@...db.de>,
	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>
Cc:	"tglx@...utronix.de" <tglx@...utronix.de>,
	"mingo@...hat.com" <mingo@...hat.com>,
	"hpa@...or.com" <hpa@...or.com>,
	"peterz@...radead.org" <peterz@...radead.org>,
	"Waiman.Long@...com" <Waiman.Long@...com>,
	"raghavendra.kt@...ux.vnet.ibm.com" 
	<raghavendra.kt@...ux.vnet.ibm.com>,
	"oleg@...hat.com" <oleg@...hat.com>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	SHARAN ALLUR <sharan.allur@...sung.com>,
	"torvalds@...ux-foundation.org" <torvalds@...ux-foundation.org>,
	"vikram.m@...sung.com" <vikram.m@...sung.com>
Subject: [RFC] arm: Add for atomic half word exchange

Yes, I will try to do that. OTOH, I saw that  there was a discussion on removal of bad_xchg() altogether. Perhaps that approach be better than adding this half word exchange?


Regards,
Sarbojit

------- Original Message -------
Sender : Arnd Bergmann<arnd@...db.de>
Date : May 19, 2015 18:51 (GMT+09:00)
Title : Re: [RFC] arm: Add for atomic half word exchange

On Tuesday 19 May 2015 09:39:33 Sarbojit Ganguly wrote:
> Since 16 bit half word exchange was not there and MCS based qspinlock by Waiman's xchg_tail() requires an atomic exchange on a half word,
> here is a small modification to __xchg() code.

We have discussed a similar patch before, see
https://lkml.org/lkml/2015/2/25/390

>  #if __LINUX_ARM_ARCH__ >= 6
> @@ -50,6 +52,23 @@
>                         : "r" (x), "r" (ptr)
>                         : "memory", "cc");
>                 break;
> +               /* 
> +                * halfword exclusive exchange
> +                * This is new implementation as qspinlock
> +                * wants 16 bit atomic CAS.
> +                */
> +       case 2:
> +               asm volatile("@ __xchg2\n"
> +               "1:     ldrexh  %0, [%3]\n"
> +               "       strexh  %1, %2, [%3]\n"
> +               "       teq     %1, #0\n"
> +               "       bne     1b"
> +                       : "=&r" (ret), "=&r" (tmp)
> +                       : "r" (x), "r" (ptr)
> +                       : "memory", "cc");
> +               break;
>         case 4: 
>                 asm volatile("@ __xchg4\n"
>                 "1:     ldrex   %0, [%3]\n"

Please try to find a way to make this compile when CONFIG_CPU_V6
is set.

Arnd