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Message-ID: <alpine.DEB.2.10.1505201454270.6658@vshiva-Udesk>
Date: Wed, 20 May 2015 15:51:19 -0700 (PDT)
From: Vikas Shivappa <vikas.shivappa@...el.com>
To: Thomas Gleixner <tglx@...utronix.de>
cc: Vikas Shivappa <vikas.shivappa@...el.com>,
Vikas Shivappa <vikas.shivappa@...ux.intel.com>,
x86@...nel.org, linux-kernel@...r.kernel.org, hpa@...or.com,
mingo@...nel.org, tj@...nel.org, peterz@...radead.org,
Matt Fleming <matt.fleming@...el.com>,
"Auld, Will" <will.auld@...el.com>, peter.zijlstra@...el.com,
h.peter.anvin@...el.com,
"Juvva, Kanaka D" <kanaka.d.juvva@...el.com>, mtosatti@...hat.com
Subject: Re: [PATCH 5/7] x86/intel_rdt: Software Cache for IA32_PQR_MSR
On Wed, 20 May 2015, Thomas Gleixner wrote:
> On Wed, 20 May 2015, Vikas Shivappa wrote:
>> On Wed, 20 May 2015, Thomas Gleixner wrote:
>>
>>> On Wed, 20 May 2015, Vikas Shivappa wrote:
>>>> On Fri, 15 May 2015, Thomas Gleixner wrote:
>> sorry, my reason was wrong though.
>>
>
>> So PERF_EVENTS cant be disabled on x86 and RDT is only in x86 && SUP_INTEL.
>
> That should have been your answer to #1, right?
yes, thats why i said '>> sorry, my reason was wrong though.' above
I thought the .config edit would have spit out an error message as the
PERF_EVENT was reselected (basically print any such dependency changes it
does when starting to compile).
I was only curious if you compiled by any chance as some of the folks were
trying to get the Intel systems with RDT..
Thanks,
Vikas
>
> Thanks,
>
> tglx
>
>
>
>
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