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Message-ID: <CAHM4w1=6mgp+gU9wUBNZg-Mpz0vOgCw1no568qLoB1X95u2YGg@mail.gmail.com>
Date:	Wed, 20 May 2015 21:12:28 +0530
From:	Pratyush Anand <pratyush.anand@...il.com>
To:	Jisheng Zhang <jszhang@...vell.com>
Cc:	Jingoo Han <jg1.han@...sung.com>,
	Bjorn Helgaas <bhelgaas@...gle.com>,
	Minghuan.Lian@...escale.com, fabrice.gasnier@...com,
	"linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
	linux-kernel@...r.kernel.org,
	"linux-arm-kernel@...ts.infradead.org" 
	<linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH v2 2/2] PCI: designware: use iATU0 for cfg and IO, iATU1
 for MEM

On Thu, Apr 30, 2015 at 1:52 PM, Jisheng Zhang <jszhang@...vell.com> wrote:
> Most transactions' type are cfg0 and MEM, so the Current iATU usage is not
> balanced, iATU0 is hot while iATU1 is rarely used. This patch refactors
> the iATU usage: iATU0 for cfg and IO, iATU1 for MEM. This allocation
> ideas comes from Minghuan Lian <Minghuan.Lian@...escale.com>:
>
>  http://www.spinics.net/lists/linux-pci/msg40440.html
>
> Signed-off-by: Jisheng Zhang <jszhang@...vell.com>

Nice optimization of resources. Thanks :)

Acked-by: Pratyush Anand <pratyush.anand@...il.com>
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