linux-kernel - [PATCH 7/9] clk: pistachio: Add a rate table for the MIPS PLL

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Date:	Thu, 21 May 2015 20:57:41 -0300
From:	Ezequiel Garcia <ezequiel.garcia@...tec.com>
To:	<linux-mips@...ux-mips.org>, <linux-kernel@...r.kernel.org>,
	"Mike Turquette" <mturquette@...aro.org>, <sboyd@...eaurora.org>
CC:	Andrew Bresticker <abrestic@...omium.org>,
	James Hartley <james.hartley@...tec.com>,
	<Govindraj.Raja@...tec.com>, <Damien.Horsley@...tec.com>,
	<cernekee@...omium.org>, James Hogan <james.hogan@...tec.com>,
	Ezequiel Garcia <ezequiel.garcia@...tec.com>
Subject: [PATCH 7/9] clk: pistachio: Add a rate table for the MIPS PLL

This commit adds a rate parameter table, which makes it possible for
the MIPS PLL to support rate change.

Signed-off-by: Govindraj Raja <Govindraj.Raja@...tec.com>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@...tec.com>
---
 drivers/clk/pistachio/clk-pistachio.c | 12 +++++++++++-
 drivers/clk/pistachio/clk.h           | 12 ++++++++++++
 2 files changed, 23 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/pistachio/clk-pistachio.c b/drivers/clk/pistachio/clk-pistachio.c
index 22a7ebd..0ac7429 100644
--- a/drivers/clk/pistachio/clk-pistachio.c
+++ b/drivers/clk/pistachio/clk-pistachio.c
@@ -145,8 +145,18 @@ static struct pistachio_mux pistachio_muxes[] __initdata = {
 	MUX(CLK_BT_PLL_MUX, "bt_pll_mux", mux_xtal_bt, 0x200, 17),
 };
 
+static struct pistachio_pll_rate_table mips_pll_rates[] = {
+	MIPS_PLL_RATES(52000000, 416000000, 1, 16, 2, 1),
+	MIPS_PLL_RATES(52000000, 442000000, 1, 17, 2, 1),
+	MIPS_PLL_RATES(52000000, 468000000, 1, 18, 2, 1),
+	MIPS_PLL_RATES(52000000, 494000000, 1, 19, 2, 1),
+	MIPS_PLL_RATES(52000000, 520000000, 1, 20, 2, 1),
+	MIPS_PLL_RATES(52000000, 546000000, 1, 21, 2, 1),
+};
+
 static struct pistachio_pll pistachio_plls[] __initdata = {
-	PLL_FIXED(CLK_MIPS_PLL, "mips_pll", "xtal", PLL_GF40LP_LAINT, 0x0),
+	PLL(CLK_MIPS_PLL, "mips_pll", "xtal", PLL_GF40LP_LAINT, 0x0,
+	    mips_pll_rates),
 	PLL_FIXED(CLK_AUDIO_PLL, "audio_pll", "audio_refclk_mux",
 		  PLL_GF40LP_FRAC, 0xc),
 	PLL_FIXED(CLK_RPU_V_PLL, "rpu_v_pll", "xtal", PLL_GF40LP_LAINT, 0x20),
diff --git a/drivers/clk/pistachio/clk.h b/drivers/clk/pistachio/clk.h
index 3bb6bbe..b5d22d6 100644
--- a/drivers/clk/pistachio/clk.h
+++ b/drivers/clk/pistachio/clk.h
@@ -121,6 +121,18 @@ struct pistachio_pll_rate_table {
 	unsigned int frac;
 };
 
+#define MIPS_PLL_RATES(_fref, _fout, _refdiv, _fbdiv,	\
+		       _postdiv1, _postdiv2)		\
+{                                                       \
+	.fref           = _fref,                        \
+	.fout           = _fout,                        \
+	.refdiv         = _refdiv,                      \
+	.fbdiv          = _fbdiv,                       \
+	.postdiv1       = _postdiv1,                    \
+	.postdiv2       = _postdiv2,                    \
+	.frac           = 0,                            \
+}
+
 enum pistachio_pll_type {
 	PLL_GF40LP_LAINT,
 	PLL_GF40LP_FRAC,
-- 
2.3.3

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