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Message-ID: <CABPqkBTwpuCstWA+PwAjTAuPX43YShwuhirfVAoO2szZnutvbg@mail.gmail.com>
Date: Fri, 22 May 2015 06:40:49 -0700
From: Stephane Eranian <eranian@...gle.com>
To: Peter Zijlstra <peterz@...radead.org>
Cc: Ingo Molnar <mingo@...nel.org>,
Vince Weaver <vincent.weaver@...ne.edu>,
Jiri Olsa <jolsa@...hat.com>,
LKML <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 02/10] perf/x86: Improve HT workaround GP counter constraint
On Fri, May 22, 2015 at 6:36 AM, Peter Zijlstra <peterz@...radead.org> wrote:
> On Fri, May 22, 2015 at 06:29:47AM -0700, Stephane Eranian wrote:
>> On Fri, May 22, 2015 at 6:25 AM, Peter Zijlstra <peterz@...radead.org> wrote:
>> > On Fri, May 22, 2015 at 06:07:00AM -0700, Stephane Eranian wrote:
>> >>
>> >> One other thing I noticed is that the --n_excl needs to be protected by the
>> >> excl_cntrs->lock in put_excl_constraints().
>> >
>> > Nah, its strictly per cpu.
>>
>> No. the excl_cntrs struct is pointed to by cpuc but it is shared between the
>> sibling HT. Otherwise this would not work!
>
> n_excl is per cpuc, see the trickery with has_exclusive vs
> exclusive_present on how I avoid the lock.
Yes, but I believe you create a store forward penalty with this.
You store 16bits and you load 32 bits on the same cache line.
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