linux-kernel - [PATCH 02/11] x86, pci: Clean up comment about buggy MMIO config space access for AMD Fam10h CPUs.

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Message-Id: <1432644564-24746-3-git-send-email-hanjun.guo@linaro.org>
Date:	Tue, 26 May 2015 20:49:15 +0800
From:	Hanjun Guo <hanjun.guo@...aro.org>
To:	Bjorn Helgaas <bhelgaas@...gle.com>, Arnd Bergmann <arnd@...db.de>,
	Catalin Marinas <catalin.marinas@....com>,
	Will Deacon <will.deacon@....com>,
	"Rafael J. Wysocki" <rjw@...ysocki.net>
Cc:	Jiang Liu <jiang.liu@...ux.intel.com>,
	Liviu Dudau <Liviu.Dudau@....com>,
	Thomas Gleixner <tglx@...utronix.de>,
	Yijing Wang <wangyijing@...wei.com>,
	Lorenzo Pieralisi <Lorenzo.Pieralisi@....com>,
	Tomasz Nowicki <tomasz.nowicki@...aro.org>,
	Suravee Suthikulpanit <Suravee.Suthikulpanit@....com>,
	Mark Salter <msalter@...hat.com>, linux-pci@...r.kernel.org,
	linux-arm-kernel@...ts.infradead.org, linux-acpi@...r.kernel.org,
	linux-kernel@...r.kernel.org, linaro-acpi@...ts.linaro.org,
	Hanjun Guo <hanjun.guo@...aro.org>
Subject: [PATCH 02/11] x86, pci: Clean up comment about buggy MMIO config space access for AMD Fam10h CPUs.

From: Tomasz Nowicki <tomasz.nowicki@...aro.org>

- fix typo
- improve explanation
- add reference to the related document

Signed-off-by: Tomasz Nowicki <tomasz.nowicki@...aro.org>
Signed-off-by: Hanjun Guo <hanjun.guo@...aro.org>
Tested-by: Suravee Suthikulpanit <Suravee.Suthikulpanit@....com>
---
 arch/x86/include/asm/pci_x86.h | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/arch/x86/include/asm/pci_x86.h b/arch/x86/include/asm/pci_x86.h
index 164e3f8..eddf8f0 100644
--- a/arch/x86/include/asm/pci_x86.h
+++ b/arch/x86/include/asm/pci_x86.h
@@ -154,10 +154,13 @@ extern struct list_head pci_mmcfg_list;
 
 /*
  * AMD Fam10h CPUs are buggy, and cannot access MMIO config space
- * on their northbrige except through the * %eax register. As such, you MUST
- * NOT use normal IOMEM accesses, you need to only use the magic mmio-config
+ * on their northbridge except through the * %eax register. As such, you MUST
+ * NOT use normal IOMEM accesses, you need to only use the magic mmio_config_*
  * accessor functions.
- * In fact just use pci_config_*, nothing else please.
+ *
+ * Please refer to the following doc:
+ * "BIOS and Kernel Developer's Guide (BKDG) For AMD Family 10h Processors",
+ * rev. 3.48, sec 2.11.1, "MMIO Configuration Coding Requirements".
  */
 static inline unsigned char mmio_config_readb(void __iomem *pos)
 {
-- 
1.9.1

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