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Message-Id: <1432749770-26133-6-git-send-email-mathieu@codeaurora.org>
Date: Wed, 27 May 2015 11:02:50 -0700
From: Mathieu Olivari <mathieu@...eaurora.org>
To: robh+dt@...nel.org, pawel.moll@....com, mark.rutland@....com,
ijc+devicetree@...lion.org.uk, galak@...eaurora.org,
mturquette@...aro.org, sboyd@...eaurora.org,
peppe.cavallaro@...com, mathieu@...eaurora.org,
agross@...eaurora.org, joshc@...eaurora.org,
architt@...eaurora.org, georgi.djakov@...aro.org,
wsa@...-dreams.de, rnayak@...eaurora.org, davem@...emloft.net,
vbridger@...nsource.altera.com
Cc: devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-clk@...r.kernel.org, netdev@...r.kernel.org
Subject: [PATCH V2 5/5] net: stmmac: ipq806x: document device tree bindings
Add the device tree bindings documentation for the QCA IPQ806x
variant of the Synopsys DesignWare MAC.
Signed-off-by: Mathieu Olivari <mathieu@...eaurora.org>
---
.../devicetree/bindings/net/ipq806x-dwmac.txt | 35 ++++++++++++++++++++++
1 file changed, 35 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/ipq806x-dwmac.txt
diff --git a/Documentation/devicetree/bindings/net/ipq806x-dwmac.txt b/Documentation/devicetree/bindings/net/ipq806x-dwmac.txt
new file mode 100644
index 0000000..6d7ab4e
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/ipq806x-dwmac.txt
@@ -0,0 +1,35 @@
+* IPQ806x DWMAC Ethernet controller
+
+The device inherits all the properties of the dwmac/stmmac devices
+described in the file net/stmmac.txt with the following changes.
+
+Required properties:
+
+- compatible: should be "qcom,ipq806x-gmac" along with "snps,dwmac"
+ and any applicable more detailed version number
+ described in net/stmmac.txt
+
+- qcom,nss-common: should contain a phandle to a syscon device mapping the
+ nss-common registers.
+
+- qcom,qsgmii-csr: should contain a phandle to a syscon device mapping the
+ qsgmii-csr registers.
+
+Example:
+
+ gmac: ethernet@...00000 {
+ device_type = "network";
+ compatible = "qcom,ipq806x-gmac";
+ reg = <0x37000000 0x200000>;
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq";
+
+ qcom,nss-common = <&nss_common>;
+ qcom,qsgmii-csr = <&qsgmii_csr>;
+
+ clocks = <&gcc GMAC_CORE1_CLK>;
+ clock-names = "stmmaceth";
+
+ resets = <&gcc GMAC_CORE1_RESET>;
+ reset-names = "stmmaceth";
+ };
--
2.1.4
--
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