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Message-Id: <1433029955-7346-8-git-send-email-albeu@free.fr>
Date: Sun, 31 May 2015 01:52:30 +0200
From: Alban Bedel <albeu@...e.fr>
To: linux-mips@...ux-mips.org
Cc: Rob Herring <robh+dt@...nel.org>, Pawel Moll <pawel.moll@....com>,
Mark Rutland <mark.rutland@....com>,
Ian Campbell <ijc+devicetree@...lion.org.uk>,
Kumar Gala <galak@...eaurora.org>,
Thomas Gleixner <tglx@...utronix.de>,
Jason Cooper <jason@...edaemon.net>,
Ralf Baechle <ralf@...ux-mips.org>,
Alban Bedel <albeu@...e.fr>,
Andrew Bresticker <abrestic@...omium.org>,
Qais Yousef <qais.yousef@...tec.com>,
Gabor Juhos <juhosg@...nwrt.org>, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: [PATCH v4 07/12] devicetree: Add bindings for the ATH79 PLL controllers
Signed-off-by: Alban Bedel <albeu@...e.fr>
---
v2: * Fixed the node names to respect ePAPR
* Fixed the missing 's' in 'fallbacks' and the 'clocks' property
v3: * Fix the compatible string for qca9550
---
.../devicetree/bindings/clock/qca,ath79-pll.txt | 33 ++++++++++++++++++++++
1 file changed, 33 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/qca,ath79-pll.txt
diff --git a/Documentation/devicetree/bindings/clock/qca,ath79-pll.txt b/Documentation/devicetree/bindings/clock/qca,ath79-pll.txt
new file mode 100644
index 0000000..e0fc2c1
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qca,ath79-pll.txt
@@ -0,0 +1,33 @@
+Binding for Qualcomm Atheros AR7xxx/AR9XXX PLL controller
+
+The PPL controller provides the 3 main clocks of the SoC: CPU, DDR and AHB.
+
+Required Properties:
+- compatible: has to be "qca,<soctype>-cpu-intc" and one of the following
+ fallbacks:
+ - "qca,ar7100-pll"
+ - "qca,ar7240-pll"
+ - "qca,ar9130-pll"
+ - "qca,ar9330-pll"
+ - "qca,ar9340-pll"
+ - "qca,qca9550-pll"
+- reg: Base address and size of the controllers memory area
+- clock-names: Name of the input clock, has to be "ref"
+- clocks: phandle of the external reference clock
+- #clock-cells: has to be one
+
+Optional properties:
+- clock-output-names: should be "cpu", "ddr", "ahb"
+
+Example:
+
+ memory-controller@...50000 {
+ compatible = "qca,ar9132-ppl", "qca,ar9130-pll";
+ reg = <0x18050000 0x20>;
+
+ clock-names = "ref";
+ clocks = <&extosc>;
+
+ #clock-cells = <1>;
+ clock-output-names = "cpu", "ddr", "ahb";
+ };
--
2.0.0
--
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