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Message-ID: <1433159614-437-1-git-send-email-vigneshr@ti.com>
Date: Mon, 1 Jun 2015 17:23:29 +0530
From: Vignesh R <vigneshr@...com>
To: Paul Walmsley <paul@...an.com>, Tero Kristo <t-kristo@...com>,
Thierry Reding <thierry.reding@...il.com>,
Rob Herring <robh+dt@...nel.org>,
Pawel Moll <pawel.moll@....com>,
Mark Rutland <mark.rutland@....com>,
Ian Campbell <ijc+devicetree@...lion.org.uk>,
Kumar Gala <galak@...eaurora.org>,
Benoit Cousson <bcousson@...libre.com>,
Tony Lindgren <tony@...mide.com>,
Russell King <linux@....linux.org.uk>,
Mike Turquette <mturquette@...aro.org>,
Stephen Boyd <sboyd@...eaurora.org>
CC: <linux-pwm@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <linux-omap@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-clk@...r.kernel.org>, Vignesh R <vigneshr@...com>
Subject: [PATCH 0/5] Add support for PWMSS on DRA7
Hi,
This patch series adds support for PWMSS on DRA7. The IP is same as that
present in AM33XX and AM43XX.
The first patch changes clock domain in which PWMSS is present
(l4per2_7xx_clkdm) to SW_WKUP. This is because legacy IPs like PWM
does'nt support HW_AUTO prorperly. Hence, switch clock domain to
SW_WKUP. This is based on the input from the hardware team.
The rest of the patches add hwmod and dt entries and enable PWMSS on
DRA7 based SoCs.
Vignesh R (5):
ARM: OMAP2+: DRA7: clockdomain: change l4per2_7xx_clkdm to SW_WKUP
ARM: OMAP2+: DRA7: Add hwmod entries for PWMSS
ARM: dts: DRA7: Add TBCLK for PWMSS
clk: ti: DRA7: Add tbclk data for ehrpwm
ARM: dts: DRA7: Add dt nodes for PWMSS
.../devicetree/bindings/pwm/pwm-tiehrpwm.txt | 8 +
.../devicetree/bindings/pwm/pwm-tipwmss.txt | 17 +-
arch/arm/boot/dts/dra7.dtsi | 69 ++++++
arch/arm/boot/dts/dra7xx-clocks.dtsi | 26 +++
arch/arm/mach-omap2/clockdomains7xx_data.c | 2 +-
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 239 +++++++++++++++++++++
drivers/clk/ti/clk-7xx.c | 3 +
7 files changed, 362 insertions(+), 2 deletions(-)
--
2.4.1
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