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Message-Id: <1433444021-22167-10-git-send-email-geert+renesas@glider.be>
Date: Thu, 4 Jun 2015 20:53:35 +0200
From: Geert Uytterhoeven <geert+renesas@...der.be>
To: Simon Horman <horms@...ge.net.au>,
Magnus Damm <magnus.damm@...il.com>,
"Rafael J. Wysocki" <rjw@...ysocki.net>,
Kevin Hilman <khilman@...nel.org>,
Ulf Hansson <ulf.hansson@...aro.org>,
Lina Iyer <lina.iyer@...aro.org>,
Mark Rutland <mark.rutland@....com>,
Pawel Moll <pawel.moll@....com>
Cc: linux-pm@...r.kernel.org, devicetree@...r.kernel.org,
linux-sh@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org,
Geert Uytterhoeven <geert+renesas@...der.be>
Subject: [PATCH/RFC 09/15] ARM: shmobile: r8a7793 dtsi: Add L1 cache information to CPU node
Describe the L1 instruction and data caches in the CPU node:
- The L1 caches for the Cortex-A15 CPU cores are organized as 16 KiB x
2 ways.
Signed-off-by: Geert Uytterhoeven <geert+renesas@...der.be>
---
arch/arm/boot/dts/r8a7793.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
index cf153b9c2367a211..a7e892fe3efa7fd3 100644
--- a/arch/arm/boot/dts/r8a7793.dtsi
+++ b/arch/arm/boot/dts/r8a7793.dtsi
@@ -38,6 +38,16 @@
< 937500 1000000>,
< 750000 1000000>,
< 375000 1000000>;
+
+ i-cache-size = <0x8000>;
+ i-cache-sets = <512>;
+ i-cache-block-size = <32>;
+ i-cache-line-size = <32>;
+ d-cache-size = <0x8000>;
+ d-cache-sets = <512>;
+ d-cache-block-size = <32>;
+ d-cache-line-size = <32>;
+ next-level-cache = <&L2_CA15>;
};
};
--
1.9.1
--
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