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Message-ID: <20150604194844.GH676@codeaurora.org>
Date:	Thu, 4 Jun 2015 12:48:44 -0700
From:	Stephen Boyd <sboyd@...eaurora.org>
To:	Ezequiel Garcia <ezequiel.garcia@...tec.com>
Cc:	linux-mips@...ux-mips.org, linux-kernel@...r.kernel.org,
	Mike Turquette <mturquette@...aro.org>,
	Andrew Bresticker <abrestic@...omium.org>,
	James Hartley <james.hartley@...tec.com>,
	James Hogan <james.hogan@...tec.com>, cernekee@...omium.org,
	Govindraj.Raja@...tec.com, Damien.Horsley@...tec.com
Subject: Re: [PATCH 3/3] clk: pistachio: Add sanity checks on PLL
 configuration

On 05/26, Ezequiel Garcia wrote:
> From: Kevin Cernekee <cernekee@...omium.org>
> 
> When setting the PLL rates, check that:
> 
>  - VCO is within range
>  - PFD is within range
>  - PLL is disabled when postdiv is changed
>  - postdiv2 <= postdiv1
> 
> Reviewed-by: Andrew Bresticker <abrestic@...omium.org>
> Signed-off-by: Kevin Cernekee <cernekee@...omium.org>
> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@...tec.com>
> ---

Applied to clk-next

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